1. Progress Report
Chester Liu
2013/7/26

2. Workstation Environment Setup
Run Ubuntu GNOME inside VMware on top of Windows 7
Installed tools
Synopsys VCS
SpringSoft Verdi
Synopsys Synplify
Synopsys Identify
Xilinx ISE 14.6
Perforce

3. WiFi Module Daughterboard
Sub-circuits
RS9110 WiFi module
UART protocol version
4 pins are brought out to the pin header
TX, RX, GND, and VDD
MAX3232
UART voltage converter for 3.3V
Power
3.3V LDO voltage regulator

4. WiFi Module Daughterboard
Simple TCP test
Hardware setup
Connect the DTB to the computer using a USB-RS232 converter
Software setup
TeraTerm terminal program
115200baud, 8N2
Result
Successfully retrieves HTTP document from Google

5. FPGA Boards Socle MDK3D Xilinx ZC706 Xilinx Virtex-5 XC5VLX330
LUTs
No 2.54mm pin header for I/O connection
Workaround using test point
Xilinx ZC706
Xilinx Zynq-7000 XC7Z045
Dual Cortex-A LUTs
On-board Digilent USB-JTAG programmer
Bootable Linux image on SD card
However, only prebuilt image (without source code) available for the time being
Only mm pin header for I/O connection
Currently no workaround for more than 8-pin I/O connection

6. FPGA Board Test Simple UART loop-back test circuit Hardware setup
One RX-to-FIFO module
One FIFO-to-TX module
Directly connect them to form a RX-FIFO-TX loop-back circuit
Source clock frequency
25MHz on MDK3D
200MHz on ZC706
Hardware setup
Connect FPGA I/O to the computer through the standalone MAX3232 circuit on the WiFi DTB
Software setup
115200baud, 8N1
Result
Terminal prints what you type

7. FPGA Board Test Hardware connection for MDK3D
Hardware connection for ZC706

8. FPGA Simulation and Implementation Environment Setup
Collection of scripts and makefiles under organized directory tree
Provide a unified simulation and implementation environment
Synthesis
Use Synplify
ISE synthesis tool’s support for newer Verilog feature is limited, such as 2D array
Identify is available
Automatically generated circuit which can record real-time signal values and dump to a waveform file
Place and route
Use ISE

9. DVC Study Read paper and Chieh-Chuan’s thesis
Trace software version DVC encoder code
Browse through the overall encode flow
Now studying CAVLC
Will work on LDPC once finishing CAVLC

10. To-do To-do Book study Design Probability Information theory H.264
Display camera image on LCD