1. Advance Skills
TYWu

2. XILINX Special Elements
The SRL16 is a very efficient way to create shift registers without using up flip-flop resources.

3. XILINX Special Elements
FPGAs:
Before writing shift register behavior it is important to recall that Virtex, Virtex-E, Virtex-II, and Virtex-II Pro have specific hardware resources to implement shift registers: SRL16 for Virtex and Virtex-E, and SRLC16 for Virtex-II and Virtex-II Pro. Both are available with or without a clock enable. The following figure shows the pin layout of SRL16E.

4. XILINX Special Elements

5. XILINX Special Elements
module srl16_ex (CLK, DIN, QOUT);
input CLK, DIN;
output QOUT;
// For RTL simulation only.
// The defparam will not synthesize.
// synthesis translate_off
defparam U0.INIT = 16’hAAAA;
// synthesis translate_on
// Static length - 16-bit SRL
SRL16 U0 (.D (DIN), .Q (QOUT), .CLK (CLK),
.A0 (1’b1), .A1 (1’b1), .A2 (1’b1), .A3 (1’b1));
endmodule

6. XILINX Special Elements
Inferring SRL16 in Verilog: Use the following coding example for FPGA Compiler II, LeonardoSpectrum, Synplify, and XST.
//This design infer 3 SRL16 with 4 pipeline delay
module srle_example (clk, enable, data_in, result);
parameter cycle=4;
parameter width = 3;
input clk, enable;
input [0:width] data_in;
output [0:width] result;
reg [0:width-1] shift [cycle-1:0];
integer i;
clk)
begin
if (enable == 1) begin
for (i = (cycle-1);i >0; i=i-1) shift[i] = shift[i-1];
shift[0] = data_in;
end
assign result = shift[cycle-1];
endmodule

7. Instantiating Global Clock Buffers
///////////////////////////////////////////////
// CLOCK_MUX_BUFG.V Version 1.2 //
// This is an example of an instantiation of //
// a multiplexing global buffer (BUFGMUX) //
// from an internally driven signal //
module clock_mux (DATA,SEL,SLOW_CLOCK,FAST_CLOCK,DOUT);
input DATA, SEL, SLOW_CLOCK, FAST_CLOCK;
output DOUT;
reg CLOCK, DOUT;
wire CLOCK_GBUF;
BUFGMUX GBUF_FOR_MUX_CLOCK (.O(CLOCK_GBUF), .I0(SLOW_CLOCK), .I1(FAST_CLOCK), .S(SEL));
(posedge CLOCK_GBUF) DOUT <= DATA;
endmodule

8. Resource Sharing module res_sharing (A1, B1, C1, D1, COND_1, Z1);
input COND_1;
input [7:0] A1, B1, C1, D1;
output [7:0] Z1;
reg [7:0] Z1;
or B1 or C1 or D1 or COND_1)
begin
if (COND_1) Z1 <= A1 + B1;
else
Z1 <= C1 + D1;
end
endmodule

9. Resource Sharing

10. Resource Sharing

11. Resource Sharing RESOURCE_SHARING Syntax Examples Verilog UCF
Specify as follows:
// synthesis attribute resource_sharing [of]
module_name [is] yes;
For a more detailed discussion of the basic Verilog syntax, see the
“Verilog” section of the “Constraint Entry” chapter.
UCF
Not applicable.

12. Tri-state buffer module three_st (T, I, O); input T, I; output O;
reg O;
or I)
begin
if (~T)
O = I;
else
O = 1'bZ;
end
endmodule

13. Tri-state Bus module mux_tbuf (A,B,C,D,E,SEL,SIG); input A,B,C,D,E;
input [4:0] SEL;
output SIG;
reg SIG;
(SEL or A)
begin
if (SEL[0]==1’b0)
SIG=A;
else
SIG=1’bz;
end
(SEL or B)
if (SEL[1]==1’b0)
SIG=B;
(SEL or C)
if (SEL[2]==1’b0)
SIG=C;
(SEL or D)
begin
if (SEL[3]==1’b0)
SIG=D;
else
SIG=1’bz;
end
(SEL or E)
if (SEL[4]==1’b0)
SIG=E;
endmodule

14. 8x4-bit Multiplier module compar(A, B, RES); input [7:0] A;
input [3:0] B;
output [11:0] RES;
assign RES = A * B;
endmodule

15. Dividers
Divisions are only supported, when the divisor is a constant and is a power of 2. In that case, the operator is implemented as a shifter; otherwise, an error message will be issued by XST.

16. Dividers module divider(DI, DO); input [7:0] DI; output [7:0] DO;
assign DO = DI / 2;
endmodule

17. Supported Feature

18. Supported Feature

20. Supported Feature

21. Supported Feature

22. Supported Feature

23. FSM

24. FSM

25. One Process module fsm (clk, reset, x1, outp); input clk, reset, x1;
output outp;
reg outp;
reg [1:0] state;
parameter s1 = 2'b00; parameter s2 = 2'b01;
parameter s3 = 2'b10; parameter s4 = 2'b11;
clk or posedge reset)
begin
if (reset)
state = s1; outp = 1'b1;
end
else
case (state)
s1: begin
if (x1==1'b1) state = s2;
else state = s3;
outp = 1'b1;
s2: begin
state = s4; outp = 1'b1;
end
s3: begin
state = s4; outp = 1'b0;
s4: begin
state = s1; outp = 1'b0;
endcase
endmodule

26. Two Processes

27. Two Processes always @(posedge clk or posedge reset) begin if (reset)
state = s1;
else
case (state)
s1: if (x1==1'b1) state = s2;
else state = s3;
s2: state = s4;
s3: state = s4;
s4: state = s1;
endcase
end
s1: outp = 1'b1;
s2: outp = 1'b1;
s3: outp = 1'b0;
s4: outp = 1'b0;

28. Three Processes

29. Three Processes always @(posedge clk or posedge reset) begin
if (reset) state = s1;
else state = next_state;
end
or x1)
case (state)
s1: if (x1==1'b1) next_state = s2;
else next_state = s3;
s2: next_state = s4;
s3: next_state = s4;
s4: next_state = s1;
endcase
s1: outp = 1'b1;
s2: outp = 1'b1;
s3: outp = 1'b0;
s4: outp = 1'b0;

30. State Encoding XST supports the following state encoding techniques
Auto
One-Hot
Gray
Compact
Johnson
Sequential
User

31. State Encoding in Foundation
One Hot
Sets the One-Hot default encoding.
Binary
Sets the binary encoding.
Zero One Hot
Sets the Zero One Hot encoding.

32. Input/Output Blocks

33. Input/Output Blocks
In Synplify, users can set xc_padtype attribute in SCOPE (Synplify’s constraint editor) or in HDL code as shown below:
module test_padtype (a, b, clk, rst, en, bidir, q);
input [3:0] a /* synthesis xc_padtype = "IBUF_AGP"*/;
input [3:0] b;
input clk, rst, en;
inout [3:0] bidir /* synthesis xc_padtype ="IOBUF_CTT" */;
output [3:0] q /* synthesis xc_padtype ="OBUF_F_12" */;

34. Port Connection Rules
input
output
input,wire,reg
input, output, net