INPUT-OUTPUT ORGANIZATION

INPUT-OUTPUT ORGANIZATION
UNIT-III INPUT-OUTPUT ORGANIZATION

List of Topics Peripheral Devices Input-Output Interface
Modes of Transfer Priority Interrupt Direct Memory Access Input-Output Processor Serial Communication Introduction to Peripheral Component Interconnect (PCI) bus.

PERIPHERAL DEVICES The input-output subsystem of a computer, referred to as I/O Provides an efficient mode of communication between the central system and the outside environment. Programs and data must be entered into computer memory for processing and results obtained from computations must be recorded or displayed for the user. The most familiar means of entering information in to a computer is through a typewriter – like keyboard. Every time a key is pressed, the terminal sends a binary coded character to the computer. When the input information is transferred to the processor via a slow keyboard, the processor(a fast device) will be idle most of the time (waiting for information to arrive). To use computer efficiently Large amount of programs and data must be prepared in advance and transmitted in to a storage medium (disks) which is then transferred in to computer memory at a rapid rate. Devices that are under the direct control of computer are designed to read information into or out of the memory unit upon command from the CPU and are considered to be part of the total computer system. Input or output devices attached to the computer peripherals.

PERIPHERAL DEVICES Types: These types may be
Input peripherals, Output peripherals & Input-output peripherals These types may be Serial, Digital & Serial or parallel Among the most common peripherals are: Keyboards, Display units & Printers Peripherals that provide auxiliary(secondary) storage for the system are Magnetic disks & Tapes

PERIPHERAL DEVICES Magnetic disks have high speed rotational surfaces coated with magnetic material. Access is achieved by moving a read-write mechanism to a track in the magnetized surface. Disks are mostly used for bulk storage of programs and data. Magnetic tapes are used to store files of data: e.g. company payroll record. Access is sequential and consists of records that can be accessed one after another as the tape moves along a stationary read-write mechanism. Features of magnetic tapes: It is one of the cheapest and slowest methods for storage (disadvantage). It can be removed when not in use (advantage). Note: Not all input comes from people and not all output is intended for people.

PERIPHERAL DEVICES ASCII Alphanumeric Characters:
Input and Output devices that communicate with people and computer are usually involved in the transfer of alphanumeric information to and from the device and the computer. The standard binary code for the alphanumeric characters is ASCII (American Standard Code for Information Interchange). It uses 7bits to code 128 characters as shown in table 7 bit of the code is designated by b1 through b7 being the most significant bit. The letter A  represented in ASCII as (column 100, row 0001). ASCII is a 7-bit code, but most computers manipulate an 8-bit quantity as a single unit called a byte Extra bit used for other purposes depending on applications – e.g. bit is set to 1 used for other symbols like Greek alphabet.

32 special printable characters such as %,*, and $
PERIPHERAL DEVICES ASCII codes contains 94 printing characters 34 nonprinting or control characters  used for various control functions. Types Format effectors Control layout of printing  include typewriter controls like backspace (BS) etc… Information separators To separate data in to divisions like paragraphs and pages  uses control characters like record separator (RS), FS etc… Communication control Useful during transmission of text between remote terminals  STX, ETX etc… 26 Upper case 26 Lower case 10 Numerals (0-9) 32 special printable characters such as %,*, and $ 94

Input – Output Interface
It Provides a method for transferring information between internal storage and external I/O devices. Peripherals connected to a computer need a special communication link for interfacing them with CPU. Communication link is used to resolve the difference that exists between the central computer and each peripheral.

Differences are shown as below:

To resolve these differences computer systems include special hardware components between CPU and peripherals to supervise and synchronize all input and output transfers. Called Interface Units Interface in digital computer is referred to as a complementary set of signal connection points between two parts of system. Types of interfaces are CPU interface that corresponds to the system bus Input-output interface that depends on the nature of input-output device. Circuit is placed in between CPU and I/O interface – meant for matching the signal formats and timing characteristics of the CPU interface to those of the input-output device interface.

The main function of input-output interface are Data conversion  refers to digital to analog signals Synchronization  refers to matching operating speeds of CPU and other peripherals Device selection  refers to selection of I/O device by CPU in a queue manner

I/O Bus and Interface Modules A typical communication link between the processor and several peripherals is shown in figure

The I/O bus consists of Data lines Address lines Control lines Each peripheral device has associated with it an interface unit Each interface decodes the address and control received from the I/O bus, interprets them for peripheral, and provides signals for the peripheral controller. It also synchronizes the data flow and supervises the transfer between peripheral and processor. Each peripheral has its own controller that operates the particular electromechanical device. Example: printer controls the paper motion, print timing and selection of printing characters. A controller may be housed separately or may be physically integrated with the peripheral.

The I/O bus from the processor is attached to all peripheral interfaces. To communicate with a particular device, the processor places a device address on the address lines. Each interface attached to I/O bus contains an address decoder that monitors the address lines. When the interface detects its own address, it activates the path between the bus lines and the device that it controls. Note:- all peripherals whose address does not correspond to the address in the bus are disabled by their interface. At the same time that the address is in the address lines, the processor provides a function code in the control lines. The interface selected responds to the function code and proceeds to execute it. Referred to as an I/O Command  four types of commands that an interface may receive Control Status Data output Data input

Control Command: Issued to activate the peripheral and to inform it what to do. Issuing control command depends on the peripheral, each peripheral receives its own sequence of control commands, depending on its mode of operation. Example: A magnetic tape unit may be instructed to backspace the tape by one record, to rewind the tape or to start the tape moving in forward direction. Status Command: Used to test various status conditions in the interface and the peripheral. Example: A computer may check the status of the peripheral before a transfer is initiated. Data Output Command: Causes the interface to respond by transferring data from the bus in to one of its registers. Example: The processor issues the data output command when the tape is in correct position. Data Input Command: Opposite to Data Output command. In this case the interface receives an item of data from the peripheral and places it in its buffer register. The processor issues a data input command when the data is available in buffer register. The interface then places the data on the data lines, where they are accepted by processor.

I/O versus Memory Bus In addition to communicating with I/O the processor must communicate with the memory unit. Like I/O bus the memory bus contains data, address and read/write control lines. There are three ways that a computer bus can be used to communicate with memory and I/O. Use two separate buses one for memory and one for I/O. In this method computer has independent sets of data, address and control buses, one for accessing memory and the other for I/O. This is done in computers that provide a separate I/O processor (IOP) in addition to CPU. Use one common bus for both memory and I/O but have separate control lines for each. Use one common bus for memory and I/O with common control lines.

Isolated versus Memory-Mapped I/O Many computers use one common bus to transfer information between a memory or I/O and the CPU. The distinction between Memory and I/O transfer is made through separate read and write lines. The CPU specifies whether the address on the address lines is for a memory word or for an interface register by enabling one of two possible read or write lines. The I/O read and I/O write control lines are enabled during a memory transfer. This configuration isolates all I/O interface addresses from the addresses assigned to memory and is referred to as the Isolated I/O method for assigning addresses in a common bus. In the isolated I/O configuration – CPU has distinct input and output instructions, and each of these instruction is associated with the address of an interface register. When the CPU fetches and decodes the operation code of an I/O instruction, it places the address associated with the instruction in to the common address lines. At the same time it enables I/O read (for input) or I/O write (for output) control line.

This informs the external components that are attached to the common bus that the address in the address lines is for an interface register and not for memory word. On the other hand when the CPU is fetching an instruction or an operand from memory, it places the memory address on the address lines and enables the memory read or memory write control line. This informs the external components that the address is for a memory word and not for an I/O interface. The isolated I/O method isolates memory and I/O addresses so that memory address values are not affected by interface address assignment since each has its own address space. The other alternative is to use the same address space for both memory and I/O. In this case computer employ only one set of read and write signals and do not distinguish between memory and I/O addresses. This configuration is referred to as memory-mapped I/O. In memory-mapped I/O organization there are no specific input or output instructions. The CPU can manipulate I/O data residing in interface registers with the same instructions that are used to manipulate memory words. Each interface is organized as a set of registers that respond to read and write requests in the normal address space.

Modes of Transfer Binary information received from an external device is usually stored in memory for later processing. Information transferred from the central computer in to an external device originates in the memory unit. The CPU merely executes the I/O instructions and may accept the data temporarily but the ultimate source or destination is the memory unit. Data transfer between the central computer and I/O devices may be handled in a variety of modes. Some modes use CPU as an intermediate path; others transfer the data directly to and from the memory unit. Data transfer to and from peripherals may be handled in one the three possible modes Programmed I/O Interrupt-initiated I/O Direct Memory Access (DMA)

Modes of Transfer Programmed I/O operations are the result of I/O instructions written in the computer program. Each data item transfer is initiated by an instruction in the program. Usually the transfer is to and from a CPU register and peripheral. Other instructions are needed to transfer the data to and from CPU and memory. Transferring data under program control requires constant monitoring of the peripheral by the CPU. Once the data transfer is initiated the CPU is required to monitor the interface to see when a transfer can again be made. In the programmed I/O method the CPU stays in program loop until the I/O unit indicates that it is ready for data transfer. This is a time consuming process since it keeps the processor busy needlessly . This can be avoided by using interrupt facility and special commands to inform the interface to issue an interrupt request signal when the data are available from the device. In the meantime CPU can proceed to execute another program. The interface meanwhile keeps monitoring the device.

Modes of Transfer When the interface determines that the device is ready for data transfer it generates an interrupt request to the computer. Up on detecting the external interrupt signal the CPU momentarily stops the task it is processing and branches to a service program to process the I/O transfer and then returns to the task it was originally performing. Transferring data under programmed I/O is between CPU and peripheral. In DMA interface transfers data into and out of memory unit through memory bus. The CPU initiates the transfer by supplying the interface with the starting address and the number of words needed to be transferred and then proceeds to execute other tasks. When transfer is made the DMA requests memory cycles through the memory bus. When requested is granted by the memory controller, DMA transfers the data directly into memory.

Modes of Transfer Interrupted-Initiated I/O
An alternative to the CPU constantly monitoring the flag is to let the interface inform the computer when it is ready to transfer data. This mode of transfer uses interrupt facility. While the CPU is running a program it does not check the flag. When the flag is set the computer momentarily interrupted from proceeding with the current program. Informed that flag has been set. CPU deviates from what it is doing to take care of input or output transfer. After the transfer is completed, the computer returns to previous program to continue what it was doing before the interrupt.

Modes of Transfer Software Considerations:
The CPU responds to the interrupt signal by storing the return address from the program counter into a memory stack and then control branches to a service routine that processes the required I/O transfer. Two methods to accomplish this: Vectored interrupt  source that interrupts supplies the branch information to the computer. Nonvectored interrupt  branch address is assigned to a fixed location in memory. Software Considerations: A computer must also have software routines for controlling peripherals and for transfer of data between the processor and peripherals. I/O routines must issue control commands to activate the peripheral and to check the device status to determine when it is ready for data transfer. Once ready, the information is transferred item by item until all data are transferred.

Modes of Transfer Many computers combine the interface logic with the requirements for DMA in to one unit and call it an I/O Processor (IOP). IOP can handle many peripherals through DMA and interrupt facility. In such a system the computer is divided into three separate modules: The memory unit The CPU The IOP

Priority Interrupt Data transfer between CPU and I/O device is initialized by the CPU. However the CPU cannot start the transfer unless the device is ready to communicate with the CPU. Readiness can be determined by an interrupt signal. CPU responds to interrupt request by storing the return address from PC into a memory stack and then the program branches to a service routine that processes the required transfer. In a typical application a number of I/O devices attached to the computer, with each device being able to originate an interrupt request. The first task of the interrupt system Identify the source of interrupt. Several sources request service simultaneously (possibility)  system has to decide

Priority Interrupt A priority interrupt is a system that establishes a priority over the various sources to find which condition is to be serviced first. The system may also find which conditions are permitted to interrupt the computer while another interrupt is being serviced. Higher priority interrupt levels are assigned to requests which, if delayed or interrupted, could have serious consequences. Disks  high priority  high speed transfers – possible Key board  low priority Higher priority devices served first. Establishing priority of simultaneous interrupts can be done by software or hardware.

Priority Interrupt A Polling procedure is used to identify the highest priority source by software means. A common branch address for all interrupts. Programs that takes care of interrupts begins at the branch address and polls the interrupt sources in sequence. Order in which they are tested determines the priority of each interrupt. Highest priority source is tested first if interrupt signal is on. Control branches to a service routine for this source. Otherwise the next lower priority source is tested and so on. Disadvantage of software method If More interrupts  time required to poll them can exceed the time available to service the I/O device. Overcome  using hardware priority interrupt unit

Priority Interrupt It functions as an overall manager in an interrupt system environment. It accepts interrupt requests from many sources, determining which incoming requests has the highest priority. Issues an interrupt request to computer based on this determination. To speed up operation, each interrupt source has its own interrupt vector to access its own service routine directly. No polling required because. Diasy –Chaining priority It consists of a serial connection of all devices that request an interrupt. Device with highest priority is placed in the first position followed by lower priority devices up to the device with lowest priority which is placed last in the chain. Priority Encoder: It is a circuit that implements the priority function. The logic of priority encoder is such that if two or more inputs arrive at the same time The input having the highest priority will take precedence.

Priority Interrupt Software Routines:
A priority interrupt system is a combination of hardware and software techniques. The computer must also have software routines for servicing the interrupt requests and for controlling the interrupt hardware registers. The following figure shows the program that must reside in memory for handling the interrupt system. Each device has its own service program that can be read through a jump (JMP) instruction stored at the assigned vector address. The symbolic name of each routine represents the starting address of the service program. The stack shown in the diagram is used for storing the return address after each interrupt.

DMA The transfer of data between a fast storage device such as magnetic disk and memory is often limited by the speed of the CPU. Removing the CPU from the path and letting the peripheral device manage the memory buses directly would improve the speed of transfer – called DMA (Direct Memory Access). During DMA transfer CPU is idle and has no control of the memory buses. DMA controller takes over the buses to manage the transfer directly between the I/O device and memory. CPU may be placed in idle state in variety of ways. One common method extensively used in microprocessors is to disable the buses through special control signals (following figure shows).

DMA BR  Bus request BG  Bus grant
Used by DMA controller to request the CPU to give control of buses. When the input is active CPU terminates the execution of current instruction and places the address bus, data bus and read and write lines into a high impedance state. BG  Bus grant CPU activates the BG output to inform the external DMA that the buses are in the high-impedance state. DMA that originated  take control of buses When DMA terminates bus transfer it disables bus request line. CPU disables the bus grant  takes control of buses & returns to normal operation

DMA When DMA takes control of bus system
It communicates with memory – transfer can be made in several ways Burst Transfer  a block sequence consisting of number of memory words is transferred in continuous burst while DMA controller is master of the memory buses. Needed for faster devices (magnetic disks) Cycle Stealing  allows the DMA controller to transfer one data word at a time after which it must return control of the buses to CPU. CPU  delays its operation for one memory cycle to allow direct memory I/O transfer to steal one memory cycle.

DMA – DMA Controller It Needs usual circuits of an interface to communicate with the CPU and I/O device. In addition – Needs Address register Word count register Specifies no. of words that must be transferred. Data transfer may done directly between device and memory under control of DMA. Set of address lines Address register and address lines are used for direct communication with the memory. The following figure show the block diagram of DMA Controller It communicates with CPU via data bus and control lines. Registers are selected by CPU through address bus by enabling DS and RS.

DMA – DMA Controller When BG = 0 CPU can communicate with DMA registers through data bus to read from or write to DMA registers. When BG = 1 CPU relinquished the buses and DMA can communicate directly with the memory by specifying an address in the address bus and activating RD or WR control. DMA communicate with external peripheral through the request and acknowledge lines DMA controller has three registers Address register Word count register control register All registers in DMA appear to CPU as I/O interface registers. Thus CPU can read from or write to DMA registers under program control via the data bus. The DMA is first initialized by CPU. Later DMA starts and continues to transfer data between memory & peripheral unit until an entire block is transferred. Initialization process  program consisting of I/O instructions that include address for selecting particular DMA registers.

DMA – DMA Controller CPU initializes the DMA by sending the following information: Starting address of memory block where Data are available (for read) Data are to be stored (for write) Stored in address register Word count  no. of words in memory block Stored in word count register Control  specify the mode of transfer such as read or write. Stored in control register A control to start DMA transfer Once DMA initialized – CPU stops communicating with DMA unless there is an interrupt or CPU wants to check how may words have been transferred

DMA – DMA Transfer The position of DMA controller among the other components in a computer system is illustrated in figure. CPU communicates with DMA through address and data buses as with any interface unit. DMA has its own address  activates DS and RS lines. CPU initializes DMA through the data bus. Once DMA receives start control command, it can start the transfer between peripheral device and memory. When peripheral device sends a DMA request, DMA controller activates BR line, informing the CPU to relinquish the buses. CPU responds with its BG line, informing DMA that its buses are disabled. DMA then puts the current value of its address register into address bus, initiates RD or WR signal and sends a DMA acknowledge to peripheral device. When Peripheral device receives acknowledge, it puts a word in the data bus (for write) or receives a word from the data bus (for read). Thus the DMA controls the read or write operations and supplies address for memory

DMA – DMA Transfer For each word that is transferred, DMA increments its address register and decrement word count register. If word count does not reach zero, DMA checks the request line coming from the peripheral. Note: For a high speed device the line will be active as soon as the previous transfer is completed. A second transfer is then initiated and the process continues until the entire block is transferred. If word count = 0 DMA stops any further transfer and removes its bus request (also informs CPU about termination by means of an interrupt). DMA transfer is very useful in many applications like: Used for fast transfer of information between magnetic disk and memory. Useful for updating the display in an interactive terminal. Typically an image of the screen display of the terminal is kept in memory which can be updated under program control.

Input – Output processor
Instead of each interface communicate with CPU, a computer may incorporate one or more external processors and assign them the task of communicating directly with all I/O devices. IOP  classified as: Processor with DMA capability that communicates with I/O devices In this configuration computer system can be divided into Memory unit Number of Processors comprised of CPU One or more IOP’s Each IOP takes care of input and output tasks – relieving the CPU from housekeeping tasks involved in I/O transfers. Example: Processor that communicates with remote terminals over telephone and other communication media in a serial fashion is called a Data Communication Processor(DCP). IOP is similar to CPU except that it is designed to handle details of I/O Processing. Unlike the DMA controller that must be set up by the CPU, IOP fetch and execute its own instructions.

IOP instructions are specifically designed to facilitate I/O transfers. In addition to arithmetic, logic, branching and code translation tasks. Block diagram of computer with two processors is shown in figure Memory units occupies a central position and can communicate with each processor by means of DMA CPU is responsible for processing data IOP provides a path for transfer of data between various peripheral devices and memory unit. CPU is usually assigned the task of initiating the I/O program From then IOP operates independent of CPU and then continues Instructions that are read from memory by an IOP are sometimes called as commands (distinguished from instructions that are read by CPU) Prepared by experienced programmers and stored in memory. CPU informs the IOP where to find the commands in memory when its time to execute the I/O program.

CPU – IOP Communication: Communication between CPU and IOP may take different forms – depending on particular computer (considered). In most of the cases memory unit acts as “message center” where each processor leaves information for the other. Example: The following figure illustrate the method by which the CPU and IOP communicates. Simplified example that omits many operating details in order to provide an overview of basic concepts

IBM 370 I/O Channel: The I/O processor in IBM 370 computer is called a channel. A typical computer system configuration includes a number of channels with each channel attached to one or more I/O devices. Three types of channels: Multiplexer channel Connected to a number of slow- and medium-speed devices Also capable of operating number of I/O devices simultaneously Selector channel Designed to handle one I/O operation at a time Used to control high speed devices Block-Multiplexer channel Combines the features of multiplexer and selector channels. Provides a connection to high speed devices, but all I/O transfers are conducted with an entire block of data as compared to a multiplexer channel which can transfer only one byte at a time. CPU communicates directly with channels through dedicated control lines and indirectly through reserved storage areas in memory.

Word formats associated with channel operation are shown in figure below: Operation Code specifies one of the eight I/O instructions: Start I/O Start I/O fast release Test I/O Clear I/O Halt I/O Halt device Test channel Store channel identification

Word formats associated with channel operation are shown in figure below: Channel status word is always stored in location 64 in memory. Key field is a protection mechanism used to prevent unauthorized access by one user to information that belongs to another user or to the operating system. Address field gives the address of the last command word used by the channel. Count show 0 if transfer completed successfully. Status field identifies the conditions in the device and channel and any errors that occurred during transfer

Word formats associated with channel operation are shown in figure below: Data address field specifies first address of memory buffer. control field gives the no. of bytes involved in transfer. Command code field specifies an I/O operation and the flag bits provide additional information for the channel. Command code field corresponds to an operation code specifies 6 types of I/O operations: Write(transfer data from memory to I/O device), Read (transfer data from I/O device to memory), Read backwards, Control, Sense (informs channel to transfer its channel status to 64 location), Transfer in channel (used instead of jump instruction)

Serial Communication Difference between IOP and DCP is
The Way that processor communicates with the I/O devices. I/O processor communicates with peripherals through a common I/O bus i.e. comprised of many data and control lines. All peripherals share common bus and use it to transfer information to and from the I/O processor. Data Communication Processor communicates with each terminal through a single pair of wires. Both data and control information are transferred in a serial fashion with the result the transfer rate is much slower. The task of DCP is To transmit and collect digital information to and from each terminal Determine – information is data or control and Responds to all requests according to predetermined established procedures. It must also communicate with CPU and memory in the same manner as any I/O processor.

Serial Communication The way that remote terminals are connected to a data communication processor is via telephone line or other public/private communication facilities. Telephones lines are designed for voice communication but computer communicates in terms of digital signals. Some sort of converters are used to convert voice communication to digital signals Modems (also vice versa) Various modulation schemes as well as different grades of communication media and transmission speeds are used. Communication line may be connected to a synchronous or asynchronous interface, depending on the transmission method of the remote terminal. Synchronous transmission does not use start-stop bits to frame characters and therefore makes more efficient use of communication link. High speed devices use synchronous transmission.

Serial Communication Contrary to asynchronous transmission, where each character can be sent separately with its own start and stop bits, synchronous transmission must send a continuous message in order to maintain synchronism. One of the functions of the data communication processor is to check for transmission errors. Error can be detected by checking the parity bit in each character received. In synchronous transmission Message consists of group of bits transmitted sequentially as a block of data. Entire block is transmitted with special control characters at the beginning and end of the block. In asynchronous Procedure used in asynchronous terminals involving a human operator is to echo the character. The character transmitted from the keyboard to the computer is recognized by the processor and retransmitted to the terminal printer.

Serial Communication Data can be transmitted between two points in three different modes: Simplex: A simplex line carries information in one direction only. Example: radio and television broadcasting Half-Duplex: It is the one i.e. capable of transmitting in both directions but data can be transmitted in only one direction at a time. Pair of wires needed for this mode. Example: modem Time required to switch a half-duplex line from one direction to other is called turnaround time. Full-Duplex: It can send and receive data in both directions simultaneously. The communication lines, modems and other equipment used in transmission of information between two or more stations is called data link. The orderly transfer of information in a data link is accomplished by set of rules that are followed by interconnecting computers and terminals called protocol.

Serial Communication Protocols are divided in to
Character oriented protocol Is based on the binary code (most commonly used in ASCII)of a character set. It is a 7 bit code with an 8th bit used for parity. The code has 128 characters of which 95 are graphics characters (include lowercase, uppercase letters, 10 numbers and variety of special symbols) and 33 are control characters. Bit oriented protocol It does not use characters in its control field and is independent of any particular code. It allows transmission of serial bit stream of any length without the implication of character boundaries. Messages are organized in a specific format called a frame. In addition to information field a frame contains address, control, and error-checking fields. Frame boundaries are determined from a special 8-bit number called a flag.

Introduction to PCI Bus
The PCI (Peripheral Component Interconnect) bus was developed as a low-cost, processor-independent bus. Housed on the motherboard of a computer and used to connect I/O interfaces for a wide variety of devices. A device connected to the PCI bus appears to the processor as if it is connected directly to the processor bus. Bus Structure: The use of the PCI bus in a computer system is illustrated in Figure The PCI bus is connected to the processor bus via a controller called a bridge. The bridge has a special port for connecting the computer’s main memory. It may also have another special high-speed port for connecting graphics devices. The bridge translates and relays commands and responses from one bus to the other and transfers data between them. Example: When the processor sends a Read request to an I/O device The bridge forwards the command and address to the PCI bus. When the bridge receives the device’s response, it forwards the data to the processor using the processor bus. I/O devices are connected to the PCI bus, possibly through ports that use standards such as Ethernet, USB, SATA, etc…

The PCI bus supports three independent address spaces: Memory I/O Configuration The system designer may choose to use memory-mapped I/O (same address space for both memory and I/O) even with a processor that has a separate I/O address space. Approach recommended by the PCI standard for wider compatibility. The configuration space is intended to give the PCI its plug-and-play capability. Data transfers on a computer bus often involve bursts of data rather than individual words. Words stored in successive memory locations are transferred directly between the memory and an I/O device such as a disk or an Ethernet connection. Data transfers are initiated by the interface of the I/O device, which acts as a bus master. The PCI bus is designed primarily to support multiple-word transfers. A Read or a Write operation involving a single word is simply treated as a burst of length one. The PCI bus uses the same lines to transfer both address and data.

Data Transfer: The bus master, which is the device that initiates data transfers by issuing Read and Write commands, is called the initiator in PCI terminology. The addressed device that responds to these commands is called a target. The main bus signals used for transferring data are listed in Table There are 32 or 64 lines that carry address and data using a synchronous signaling scheme A complete transfer operation on the PCI bus, involving an address and a burst of data, is called a transaction.

Device Configuration: When an I/O device is connected to a computer, several actions are needed to configure both the device interface and the software that communicates with it. Like USB, PCI has a plug-and-play capability that greatly simplifies this process. In fact, the plug-and-play feature was pioneered by the PCI standard. A PCI interface includes a small configuration ROM memory that stores information about the I/O device connected to it. The configuration ROMs of all devices are accessible in the configuration address space, where they are read by the PCI initialization software whenever the system is powered up or reset. By reading the information in the configuration ROM, the software determines whether the device is a printer, a camera, an Ethernet interface, or a disk controller. It can further learn about various device options and characteristics.

Devices connected to the PCI bus are not assigned permanent addresses that are built into their I/O interface hardware. Instead, device addresses are assigned by software during the initial configuration process. This means that when power is turned on, devices cannot be accessed using their addresses in the usual way, as they have not yet been assigned any address. A different mechanism is used to select I/O devices at that time.

A computer bus is used to transfer data from one location or device on the motherboard to the central processing unit where all calculations take place. Two different parts of a Bus Address bus-transfers information about where the data should go Data bus-transfers the actual data History of PCI bus Introduced by Intel in 1992 PCI(Peripheral Component Interconnect) bus is based on ISA (Industry Standard Architecture) Bus and VL (Video Electronics Standard Association Local or VESA Local) Bus PCI provides direct access to system memory for the devices that are connected to the bus which is then connected through a bridge that connects to the front side bus. This configuration allowed for higher performance without slowing down the processor

Three features that makes PCI bus one of the fastest I/O bus used today Burst Mode: allows multiple sets of data to be sent Full Bus Mastering: the ability of devices on the PCI bus to perform transfers directly High Bandwidth Options: allows for increased speed of the PCI

Introduction to PCI Bus – comparison with other buses
Bus Type Bus Width Bus Speed MB/sec Advantages Disadvantages ISA 16 bits 8MHz 16 MBps low cost, compatibility, widely used low speed, Jumpers & DIP switches. becoming obsolete PCI 64 bits 133 MHz 1 GBps very high speed, Plug & Play, dominant board-level bus incompatible with older systems, can cost more CompactPCI 33MHz 132 MBps designed for industrial use, hot swapping/Plug & Play, ideal for embedded systems lower speed than PCI, need adapter for PC use, incompatible with older systems

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