1. UNIT VIII: CMOS TESTING
VLSI Design
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VLSI Design

2. Outline Introduction Testing Fault Models
Logic Verification
Silicon Debug
Manufacturing Test
Fault Models
Observability and Controllability
Design for Test
Scan
BIST
Boundary Scan
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3. Definition of Testing
A known input stimulus is applied to a unit in a known state, and a known response can be evaluated.
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4. VLSI Realization Process
Customer’s need
Determine requirements
Write specifications
Design synthesis and Verification
Test development
Fabrication
Manufacturing test
Chips to customer
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5. Chip Manufacturing Process
Silicon ingot
Slicer
Blank wafers
20 to 30 processing steps
8-12 in diameter
12-24 in long
< 0.1 in thick
Patterned wafer
Dicer
Individual dies
Die
Tester
Tested dies
Bond die to
package
Packaged dies
Part
Tested Packaged dies
Ship to
Customers
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VLSI Design

6. System Arch 2008 (Fire Tom Wada)
Chip photo
SoC
Flash Memory
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VLSI Design
2018/7/3
System Arch (Fire Tom Wada)

7. If anything can go wrong, it will. Murphy’s Law
FAULTS
If anything can go wrong, it will.
Murphy’s Law

8. Testing Testing is one of the most expensive parts of chips
Logic verification accounts for > 50% of design effort for many chips
Debug time after fabrication has enormous opportunity cost
Shipping defective parts can sink a company
Example: Intel FDIV bug
Logic error not caught until > 1M units shipped
Recall cost $450M (!!!)
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VLSI Design

9. Logic Verification Does the chip simulate correctly? Ex: 32-bit adder
Usually done at HDL level
Verification engineers write test bench for HDL
Can’t test all cases
Ex: 32-bit adder
Test all combinations of corner cases as inputs:
0, 1, 2, 231-1, -1, -231, a few random numbers
Good tests require ingenuity
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VLSI Design

10. Silicon Debug Test the first chips back from fabrication
If you are lucky, they work the first time
If not…
Logic bugs vs. electrical failures
Most chip failures are logic bugs from inadequate simulation
Some are electrical failures
Crosstalk
Dynamic nodes: leakage, charge sharing
Ratio failures
A few are tool or methodology failures (e.g. DRC)
Fix the bugs and fabricate a corrected chip
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11. “If you don’t test it, it won’t work! (Guaranteed)”
Think about testing from the beginning
Simulate as you go
Plan for test after fabrication
“If you don’t test it, it won’t work! (Guaranteed)”
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VLSI Design

12. Defects Defects: physical problems that occur in silicon
Common Silicon CMOS defects:
Gate-oxide shorts
Insufficient doping
Process or mask errors
Open and plugged vias
Short to power (Vdd) or Ground (Vss)
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13. Defects
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14. 23/03/2009
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15. LTX FUSION HF ATE
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16. Wafer of Pentium 4 Processors
8 inches (20 cm) in diameter
Die area is 250 mm2
55 million transistors per die
0.18 μm technology
Size of smallest transistor
Improved technology uses
0.13 μm and 0.09 μm
Dies per wafer = 169
When yield = 100%
Number is reduced after testing
Rounded dies at boundary are useless
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VLSI Design

17. Effect of Die Size on Yield
Good Die
Defective Die
Dramatic decrease in yield with larger dies
Yield = (Number of Good Dies) / (Total Number of Dies)
Die Cost = (Wafer Cost) / (Dies per Wafer  Yield)
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18. Verification vs. Test Verification Test
Verifies correctness of design.
Performed by simulation, formal methods.
Performed once prior to manufacturing.
Responsible for quality of design.
Verifies correctness of manufactured hardware.
Two-part process:
1. Test generation: software process executed once during design
2. Test application: electrical tests applied to hardware
Test application performed on every manufactured device.
Responsible for quality of devices.
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19. Testing Procedure: Apply input vectors one at a time
Examine each resulting output vector
Compare value to "known good" value
If different, chip is faulty
Naïve approach to testing:
Use all possible input vectors (2n for n inputs)
Impractical for all but very small circuits
Alternative approach:
Model things that can go wrong in design as faults
Find test vectors that expose faults
Find shortest set of vectors that expose all faults
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20. Why Test at the Chip Level?
Rule of Thumb: A test escape at one level of packaging costs ten times more to detect at the next higher level of packaging.
Moral: Detect failure at the lowest package level.
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21. Main Difficulties in Testing
Miniaturization Physical access difficult or impossible.
Increasing complexity Large amount of test data.
Number of access ports remains constant Long test application time.
Testing accounts up to 50% of product development efforts.
The key to successful testing lies in the design process.
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22. Main Difficulties in Testing (Cont..)
VLSI circuits are difficult to test due to their inherent complexity and pin limitations
Testability can be enhanced by DFT (Design For Testability) methods like scan design and BIST (Built In Self Test).
Current logic BIST methods lack generality and often have high overhead
New and better methods are needed!
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23. Testing Challenges (1) Increasing Level of Integration
Testing requires control and observation of signals in the circuit from its pins
Solution: Use DFT to increase controllability and/or observability of signals in the test mode.
As the technology advances, one can buy a lot more powerful chip, with an exponentially increasing number of gates, for the same price. However the cost of testing does not go down (in fact increases) therefore it becomes an increasingly significant cost of production.
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24. Testing Challenges (2) Rising Cost of ATE
ATEs have expensive pin electronics to be able to place sharply rising/falling signals precisely at high clock speeds.
Without cost-cutting measures the cost of testing could easily exceed the cost of manufacturing.
Primary Solution: BIST (but also higher levels of fault modeling and greater use of functional tests)
As the technology advances, one can buy a lot more powerful chip, with an exponentially increasing number of gates, for the same price. However the cost of testing does not go down (in fact increases) therefore it becomes an increasingly significant cost of production.
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25. Inadequate Fault Modeling
Testing Challenges (3)
Inadequate Fault Modeling
A new technology (e.g. when going from 90 nm to 65 nm feature size) can introduce new types of likely defects that are not modeled by the existing fault models
Solution: No easy general solution.
As the technology advances, one can buy a lot more powerful chip, with an exponentially increasing number of gates, for the same price. However the cost of testing does not go down (in fact increases) therefore it becomes an increasingly significant cost of production.
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26. High coverage of real defects Short testing time Easy test generation
Testing Goals
High coverage of real defects
Short testing time
Easy test generation
Fault diagnosis
Design for testability (DFT) makes it easier to produce high-quality tests
Built-in self-test (BIST)
As we have seen, many types of testing happen during the design, manufacturing, and field operation. Therefore, the goals of testing depend on the context of testing. Here is a summary list of goals of testing that apply to different contexts.
The first items states the goal for the quality of tests for manufacturing tests. DFT may be helpful in realizing this goal. The second item relates to process characterization and field testing. The third through sixth items are aimed at simplifying the actual process of test application. BIST also aims at eliminating or simplifying the test application process.
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27. Tools for Testing Automatic Test Pattern Generation (ATPG)
Searches for a test for every possible fault
Attempts to minimize total number of vectors
Fault Simulator
Simulates response of faulty circuit to a set of test vectors
Measures fault coverage for a given set of test vectors
Design-for-Testability, Built-In Self Test
Ways to make testing easier, especially for sequential circuits
More about these later
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28. Fault Coverage
Used as measure of test quality
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29. Observability & Controllability
Controllability: ease of forcing a node to 0 or 1 by driving input pins of the chip
Observability: ease of observing a node by watching external output pins of the chip
Combinational logic is usually easy to observe and control
Finite state machines can be very difficult, requiring many cycles to enter desired state
Especially if state transition diagram is not known to the test engineer
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30. Testing Categories Functionality tests Manufacturing tests
Done at each level of hierarchy (software+model) Higher levels of abstraction  faster
Use diagnostic reasoning to find the bug
Manufacturing tests
Performed on the final product (wafer or package)
Transistor-level simulation and testing
“Are there any disconnected wires?” “Any layer-to-layer shorts?” “Is the product tolerant to Vdd variations?”
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31. Manufacturing Test
A speck of dust on a wafer is sufficient to kill chip
Yield of any chip is < 100%
Must test chips after manufacturing before delivery to customers to only ship good parts
Manufacturing testers are
very expensive
Minimize time on tester
Careful selection of
test vectors
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32. Manufacturing Test Goals
Make testing fast
Provide controllability and observability
Controllability: ability to set internal nodes to desired values
Observability: ability to read internal node values
Challenge:
Limited number of pins
Some states might be impossible to generate
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33. Combinational Sequential Types of Circuits
2N inputs required to exhaustively test
Sequential
2M+N inputs required to exhaustively test
If each test vector takes 1ms, for M=50 and N=25, need 1 billion years to test!
Combinational
Logic N K
Combinational
Logic N K M M
Registers
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34. Testing Sequential Logic
Input vector sequence to get circuit into correct state and then another sequence to get result to a primary output
Make some state bits controllable and observable requiring less depth in sequence of input vectors
Make all state bits controllable and observable reducing problem to one of combinational circuit testing
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35. The Chip Testing Process
Expected Responses
Tests
ATE
Test
Responses R
Patterns T
Comparator
Unit
Under
(UUT)
Pass: R=R’
Fail: otherwise R’
This is a schematic view of external testing during the manufacture of a chip. The automatic test equipment is an expensive device because it must be able to store and apply the test patterns at a very high speed to the unit under test. Preferably, the speed should be the same as one for which the device is designed.
In the next few slides we will define the various problems related to testing in terms of the requirements implicit in this view.
ATE: Automatic Test Equipment
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36. Test Generation and Fault-Coverage Analysis
Obtain a sequence of test patterns with desirable fault coverage.
Determine the expected response of the UUT to the test sequence.
Test
Responses R
Comparator
Pass: R=R’
Fail: otherwise R’
UUT
Expected Responses
Once a universe of target faults is known the test generation process can proceed. It involves producing a set of test sequences with an acceptable fault coverage. The set of test sequences, along with their expected response, define the test.
During actual testing the expected responses are stored in the ATE along with the test sequences. The ATE has the capability of applying the stored test sequences, capturing the response, and comparing it against the stored expected response. All of this should be completed in relatively short time so that the device can be tested at a high speed.
Test
Patterns T
Tests
ATE
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37. Design for Testability (DFT)
Design/modify the circuit so that it is easier to test.
Test
Responses R
Comparator
Pass: R=R’
Fail: otherwise R’
Expected Responses
UUT
Test
Patterns T
Because of the difficulty and cost of testing, it is often necessary to invest in extra logic in the circuit with the sole purpose of enhancing its testability. We will discuss in some detail the design for testability schemes that are commonly used.
DFT
Overhead
Tests
ATE
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38. Self Testing Built-in self test (BIST)
Chip itself generates test vectors (internally)
Dedicated sub-circuit to generate pseudo-random test vectors
Use “linear feedback shift register (LFSR)” to generate test vectors
Use signature to check the integrity
Apply sequences of input vectors and combine the output into a signature
Shift in initial seed and shift out the signature
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39. DFT Approaches Ad Hoc Design Rules Control/test point insertion
Circuit restructuring, e.g. feedback control
Special timing considerations
Systematic Design Methods
Compact testing (signature analysis)
Scan design
-- Carefully select control/test points for insertion
-- Allow feedback paths to be opened or closed
-- Avoid asynchronous circuits and provide access to clock signals.
Regular structures.
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40. Fault Models

41. Faults Stuck-at-0 (SA0), stuck-at-1 (SA1) Bridging (shorting)
Node tied to Vdd or GND
Bridging (shorting)
Two wires tied together on one or more layers
Stuck-open
Break in a wire disconnects two wires
Delay faults
Parameter variations slow down a gate
Path-delay faults
Cumulative delay faults along a path
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VLSI Design

42. Stuck-At Faults How does a chip fail? A simpler model: Stuck-At
Usually failures are shorts between two conductors or opens in a conductor
This can cause very complicated behavior
A simpler model: Stuck-At
Assume all failures cause nodes to be “stuck-at” 0 or 1, i.e. shorted to GND or VDD
Not quite true, but works well in practice
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43. Fault Models - Stuck-at-0/1
Assume that every fault forces a gate output to be
Always zero - stuck-at-0
Always one - stuck-at-1
Testing procedure: for each node in a design
Assume that node is S-A-0
Find a test that reveals this fault
Assume this node is S-A-1
For each circuit node
One test vector may detect more than one fault!
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44. Stuck-At Faults in Gates
a b OK SA0 SA1
a b OK SA0 SA1
NAND
NOR
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45. Testing Simple Gates for Stuck-At Faults
Assume gate output is S-A-0
Apply a test vector that should generate a 1
If output is 0, then gate is faulty!
Assume gate output is S-A-1
Apply a test vector that should generate a 0 output
If output is 1, then gate is faulty!
NAND Gate:
Test for S-A-0 with inputs: , 01, or 10
Test for S-A-1 with inputs: 11
NOR Gate:
Test for S-A-0 with inputs:
Test for S-A-1 with inputs:
01, 10, or 11
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46. More about Stuck-At Fault Models
Drawback: not all real faults have this behavior!
Open circuit - may float between values
Short circuit - may change as shorted output changes
Drawback: we may more than a single fault
Even so, stuck-at fault models are used extensively
Easier to work with than other models
Shown to give good results even for non-stuck-at faults
Alternative: stuck-open model (see book)
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47. Fault Models a, g : x1 sa1 b : x1 sa0 or a x2 sa0 g b
Stuck-at covers most of the faults
Shown: short (a,g), open (b)
a, g : x1 sa1
b : x1 sa0 or
x2 sa0 Z a x1 g x3 b x2
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[©Prentice Hall]

48. Fault Models Stuck-at – open does not cover all faults Other options:
Example: Sequential effect:
Needs two vectors to detect (1,1) (1,0)
Other options:
Use stuck-open or stuck-short models
Problem: too expensive!
x1 x2 Z
0 x 1
1 1 0
1 0 Zn-1 x2 x1 Z x1 x2
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[©Prentice Hall]

49. Generating and Validating Test Vectors
Automatic test-pattern generation (ATPG)
For given fault, determine test (aka excitation) vector that will propagate error to observable output
Most available tools: combinational networks only
Fault simulation
Determine minimal test vectors that will sensitize circuit to the fault
Simulates correct network in parallel with faulty networks
Structure of logic may make some faults untestable
Both require adequate models of faults in CMOS integrated circuits
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50. PRSG (Pseudo-Random Sequence Generator)
Linear Feedback Shift Register
Shift register with input taken from XOR of state
Step Q
111 1 2 3 4 5 6 7
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51. PRSG Linear Feedback Shift Register
Shift register with input taken from XOR of state
Step Q
111 1
110 2 3 4 5 6 7
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52. PRSG Linear Feedback Shift Register
Shift register with input taken from XOR of state
Step Q
111 1
110 2
101 3 4 5 6 7
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53. PRSG Linear Feedback Shift Register
Shift register with input taken from XOR of state
Step Q
111 1
110 2
101 3
010 4 5 6 7
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54. PRSG Linear Feedback Shift Register
Shift register with input taken from XOR of state
Step Q
111 1
110 2
101 3
010 4
100 5 6 7
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55. PRSG Linear Feedback Shift Register
Shift register with input taken from XOR of state
Step Q
111 1
110 2
101 3
010 4
100 5
001 6 7
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56. PRSG Linear Feedback Shift Register
Shift register with input taken from XOR of state
Pseudo-Random Sequence Generator
Step Q
111 1
110 2
101 3
010 4
100 5
001 6
011 7
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57. PRSG Linear Feedback Shift Register
Shift register with input taken from XOR of state
Step Q
111 1
110 2
101 3
010 4
100 5
001 6
011 7
111 (repeats)
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58. Test Vector Generation: Path Sensitization
Work forward and backward from node of interest to determine values of inputs to test for fault
At the site of the fault, assign a logical value complementary to the fault
Select a path from the circuit inputs through the site of the fault to an output, the path is sensitized if the inputs to the gates along the path are set so as to propagate the value at the fault site
Determine the primary inputs that will produce the required values at the gate inputs as determined above
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[©Hauck]

59. Automatic Test Pattern Generation
Eases generation of test vectors.
Reduces cost of test
More efficient test vectors
Reduction in cycle time
Provides a deterministic quality metric.
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60. ATPG
no error
error /1 
1/0
1/0 1 1 1
Could we check for a stuck at one error at a (s-a-1(a)) ?
Solution (just guessing):
f='1' if there is an error
 a='0', b='0' in order to have f='0' if there is no error
g='1' in order to propagate error
c='1' in order to have g='1' (or set d='1')
e='1' in order to propagate error
i='1' if there is no error & i='0' if there is error
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61. Path Sensitization Example
Trigger the fault
Make it propagate to output
sa0 1
Fault enabling 1
Out
Fault propagation
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[©Prentice Hall]

62. Level Sensitive Scan Design (LSSD)
Known as scan-based test
Scan path (shift register) links all state elements in circuit
Observe and control all states
Requires 3 extra pins and a bit more logic in FFs
All tests become combinational
Very slow — shift in test vector and shift out output vector serially — partial scan paths only use necessary amount
Easy to extend to system level
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[©Hauck]

63. Using Scan Design Shift in to set FF values
Shift out to read FF values
Scan variations
Full scan - require scan in all flip-flops
Partial scan - require scan in some flip-flops
Boundary scan - use scan for block I/Os (often used in board-level test)
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64. Scan Flip-Flop Scan-out Scan-out Scan-in Scan-in Din Din Dout Dout 1
Din
Dout
Dout
Scan-in
Scan-in 1
Test
Test
Clock
Clock
Explain how it works. The left hand picture shows the schematic symbol for a scan FF. The right hand one shows a possible implementation. Note that other implementations are also possible. For example, the LSSD latch of IBM.
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65. Scan design
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66. Scan Based Test Register Combinational Logic A B Test N cycles scan in
Out In
ScanOut
ScanIn
Combinational
Logic A B
Test
N cycles scan in
N cycles scan out
1 cycle
evaluation f1 f2
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67. Scan-Based Test Operation
Latch
Out0
In0
test
Scan In
Out1
In1
Out2
In2
Scan
Out
Out3
In3
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68. Limitations of a single serial scan chain
For chips with a large number of flop-flops, serial shifts can take a quite long time.
Hence, it becomes necessary to provide several scan chains.
Trying to avoid serial shifts by generating test patterns internally and by also storing the results internally.
Compaction of circuit response in a signature. Shifting the entire result out becomes obsolete, we just shift out the signature.
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69. Signature analysis n-bit shift register XOR
Response of circuit to sequence of test patterns compacted in a signature. Only this signature is compared to the golden reference.
Exploit an n-bit signature register as well as possible:  try to use all values possible for that registers!
In practice, we use shift-registers with linear feedback:
n-bit shift register
XOR
Response of circuit to sequence of test vectors
Signature
Using proper feedback bits, all values possible for the register can be generated.
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70. Built-in Self-Test (BIST)
Include test-vector generation and response-analysis circuitry within the chip.
Expected Responses
Tests
BIST Logic
Test
Responses R
Patterns T
Comparator
Unit
Under
Pass: R=R’
Fail: otherwise R’
Chip Boundary
Built-in self-test is a DFT scheme in which all the components of an external tester are essentially integrated into the chip so that either an external tester is eliminated or a much simpler one will do.
BIST is currently used extensively in memory designs but not as much in logic designs.
This is likely to change because the economics of testing deep-submicron devices favors a built-in tester over an external tester.
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VLSI Design 70 70

71. Built-In Self-Test (BIST)
Self-test logic, consisting of pattern generator, response analyzer & test manager, is built into the chip.
The test manager executes the self-test and accumulates its result for transmission to an an external pin or higher package-level test manager.
Chip
Board
System
Test
Manager
Pattern
Generator
CUT
Response
Analyzer
Standards like boundary scan provide a systematic way for implementing the idea of a hierarchical BIST. Among other things, boundary scan allows full access to the pins at one level of packaging at the next level without requiring internal probing.
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72. Built-In Self Test (BIST)
Goal: provide limited testing within the chip itself
Typical approach: use Linear Feedback Shift Register (LFSR)
Structure: shift register with exclusive-OR feedback
"Pseudo-random" state sequence
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73. BIST (cont'd) Applications of LFSRs
Generate pseudo-random test vectors for self-test
Use as signature analyzer to compress output vectors
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74. BIST (cont'd) Applications of LFSRs
Generate pseudo-random test vectors for self-test
Use as signature analyzer to compress output vectors
LFSR
Signature Analyzer
Circuit Under Test
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75. BIST: Signature Analysis
Compress the output vector
Time compression (count # of transitions)
OR: compute output parity vector
Example: time compression: In
Counter R
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[©Prentice Hall]

76. BIST Hardware Structures
Response Compressor:
XOR Trees
-Level Counter
Transition Counter
Pattern Generators:
LFSR
Binary Counter
XOR Trees
Note that any PG can be used in combination with any RA listed in the two columns.
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77. Replacing serially shifted test pattern by pseudo random test patterns
Shifting in test patterns can be avoided if we generate (more or less) all possible test patterns internally with a pseudo-random test pattern generator.
Pseudo-random test pattern generator
DUT
Signature analysis register
Compare with reference
Effect of pseudo random numbers on coverage to be analyzed.
Signature analysis register shifted-out at the end of the test.
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78. Boundary Scan Interface
Boundary scan is accessed through five pins
TCK: test clock
TMS: test mode select
TDI: test data in
TDO: test data out
TRST*: test reset (optional)
Chips with internal scan chains can access the chains through boundary scan for unified test strategy.
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79. Printed-circuit board
Boundary Scan (JTAG)
Printed-circuit board
Logic
Packaged IC
Normal connections
Scan-in si so
Scan-out
scan path
Bonding Pad
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[©Prentice Hall]

80. JTAG (Boundary scan)
JTAG defines a 4..5-wire serial interface to access complex ICs .. Any compatible IC contains shift registers & FSM to execute the JTAG functions.
TDI: test data in; stored in instruction register or in one of the data registers. TDO: test data out TCK: clock TMS: controls the state of the test access port (TAP). Optional TRST* is reset signal.
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81. JTAG (Boundary scan) (2)
Defines method for setting up a scan chain on a PCB
Source: com/brochure.php
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82. The TAP Signals
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83. Top-Level View of the TAP Controller
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84. 23/03/2009
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85. Linear-Feedback Shift Register (LFSR)
1 0 0
0 1 0
1 0 1
1 1 0
1 1 1
0 1 1
0 0 1
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86. Built-in Logic Block Observation (BILBO)D0 D1 D2 B0 B1
ScanOut
ScanIn R R R S0 S1 S2
Introduced in 1979
Same hardware used for:
Pattern generation
Signature Analysis
Normal registers
Scan registers
Input data (Di) is XORed with the value of LFSR, acting as a seed B0 B1
Operation mode 1 1
Normal
Scan 1
Pattern generation or signature analysis 1
Reset
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[©Prentice Hall]

87. BILBO – Pattern GenerationD0 =1 D1 D2
B0=1
B1=0
ScanOut
ScanIn R R R S0 S1 S2
Pattern generation mode
Set Di=1  XORs become NOT gates and negate the NOR gates  normal LFSR
Signature analysis mode
Let Di’s pass through. The signature is not very straightforward, but traceable B0 B1
Operation mode 1
Pattern generation or signature analysis
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88. BILBO – Pattern Generation vs. Signature Analysis
In addition to the BILBO circuit shown in two slides ago, you may need some extra logic (e.g., multiplexers) that send either Di’s or 1’s
Pattern generation
simple LFSR
Signature analysis
Complex
But we can simulate and predict the correct values
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89. BILBO Application Operation: Seed sent in using the scan chain
Comb
Logic 1
BILBO 2
Logic 2
BILBO 3
Logic 3
BILBO 4
Logic 4
BILBO 5 in
out
Scan in
Scan out
Operation:
Seed sent in using the scan chain
Even BILBOs operate in pattern gen mode, odd ones in signature analysis
After a complete cycle (or desired # of cycles), odd BILBO values read through scan out
The same process repeats, this time with even BILBOs in signature analysis, odd ones in pattern generation
Feedback between different combination logics also possible, but treated as new comb inputs
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VLSI Design

90. Typical application DUT-1
Bilbo-1 (generates pseudo-random test patterns)
Bilbo-2 (compresses response)
DUT-2
Compressed response shifted out of Bilbo-2 & compared to known „golden“ reference response.
Roles of Bilbo-1 and 2 swapped for testing DUT-1
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VLSI Design

91. Self-test Rapidly becoming more important with increasing
chip-complexity and larger modules
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VLSI Design

92. Patterns: Writing/Reading 0s, 1s,
Memory Self-Test
FSM
Data in
Memory Under Test
Signature Analysis
Data out
Address & R/W Ctrl
Patterns: Writing/Reading 0s, 1s,
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VLSI Design
[©Prentice Hall]

93. Summary Test Design for Test (DFT) Fault model
TPG (Test Pattern Generation)
Application of test patterns
Checking the results
Fault coverage
Fault simulation for computing coverage
Design for Test (DFT)
Scan path, Boundary scan
Signature analysis,
Pseudo random patterns, BILBO
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VLSI Design

94. References
Principles of CMOS VLSI Design - Weste and Eshraghian, Pearson Education,
Digital Integrated Circuits - John M. Rabaey, PHI,
Essentials of VLSI circuits and systems – Kamran Eshraghian, Eshraghian Dougles and A. Pucknell,
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VLSI Design

95. If you are successful, it is because some where, some time, someone gave you a life or an idea that started you in the right direction. ...
Remember that you are indebted to life until you help some less fortunate person, just as you were helped…..
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VLSI Design

96. How do we guard the sense of value? We can do so by three things..
By constant discrimination between the real and the unreal..
By keeping ourselves busy doing those things that we have decidedly accepted as beneficial..
By avoiding idle curiosity about the things which do not concern our main pursuit in our life….
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VLSI Design

97. That’s ALL Folks..! .