XU, Qiang 徐強 [Adapted from UC Berkeley’s D. Patterson’s and

CENG/CSCI 3420 Computer Organization and Design Spring 2014 Lecture 03: Arithmetic for Computers
XU, Qiang 徐強 [Adapted from UC Berkeley’s D. Patterson’s and from PSU’s Mary J. Irwin’s slides with additional credits to Y. Xie]

Review: VHDL Supports design, documentation, simulation & verification, and synthesis of hardware Allows integrated design at behavioral and structural levels Basic structure Design entity-architecture descriptions Time-based execution (discrete event simulation) model Entity == External Characteristics Design Entity-Architecture == Hardware Component Architecture (Body ) == Internal Behavior or Structure

Review: Entity-Architecture Features
Entity defines externally visible characteristics Ports: channels of communication signal names for inputs, outputs, clocks, control Generic parameters: define class of components timing characteristics, size (fan-in), fan-out Architecture defines the internal behavior or structure of the circuit Declaration of internal signals Description of behavior collection of Concurrent Signal Assignment (CSA) statements (indicated by <=); can also model temporal behavior with the delay annotation one or more processes containing CSAs and (sequential) variable assignment statements (indicated by :=) Description of structure interconnections of components; underlying behavioral models of each component must be specified

Arithmetic Where we've been What's up ahead Abstractions
Instruction Set Architecture (ISA) Assembly and machine language What's up ahead Implementing the architecture (in VHDL) zero ovf 1 1 A 32 ALU result 32 B 32 4 m (operation)

ALU VHDL Representation
entity ALU is port(A, B: in std_logic_vector (31 downto 0); m: in std_logic_vector (3 downto 0); result: out std_logic_vector (31 downto 0); zero: out std_logic; ovf: out std_logic) end ALU; architecture process_behavior of ALU is . . . begin ALU: process(A, B, m) result := A + B; end process ALU; end process_behavior;

Machine Number Representation
Bits are just bits (have no inherent meaning) conventions define the relationships between bits and numbers Binary numbers (base 2) - integers 0000 -> > > > > > . . . in decimal from 0 to 2n-1 for n bits Of course, it gets more complicated storage locations (e.g., register file words) are finite, so have to worry about overflow (i.e., when the number is too big to fit into 32 bits) have to be able to represent negative numbers, e.g., how do we specify -8 in addi $sp, $sp, -8 #$sp = $sp - 8 in real systems have to provide for more than just integers, e.g., fractions and real numbers (and floating point) and alphanumeric (characters)

MIPS Representations 32-bit signed numbers (2’s complement): two = 0ten two = + 1ten two = + 2ten ... two = + 2,147,483,646ten two = + 2,147,483,647ten two = – 2,147,483,648ten two = – 2,147,483,647ten two = – 2,147,483,646ten ... two = – 3ten two = – 2ten two = – 1ten What if the bit string represented addresses? need operations that also deal with only positive (unsigned) integers maxint minint

Two's Complement Operations
Negating a two's complement number – complement all the bits and then add a 1 remember: “negate” and “invert” are quite different! Converting n-bit numbers into numbers with more than n bits: MIPS 16-bit immediate gets converted to 32 bits for arithmetic sign extend - copy the most significant bit (the sign bit) into the other bits > > sign extension versus zero extend (lb vs. lbu)

Design the MIPS Arithmetic Logic Unit (ALU)
32 m (operation) result A B ALU 4 zero ovf 1 Must support the Arithmetic/Logic operations of the ISA add, addi, addiu, addu sub, subu mult, multu, div, divu sqrt and, andi, nor, or, ori, xor, xori beq, bne, slt, slti, sltiu, sltu Tradeoffs of cost and speed based on frequency of occurrence, hardware budget Immediate can be negative in addiu and it is simply an addi counterpart that ignors overflow. With special handling for sign extend – addi, addiu, slti, sltiu zero extend – andi, ori, xori Overflow detected – add, addi, sub

MIPS Arithmetic and Logic Instructions
31 25 20 15 5 R-type: op Rs Rt Rd funct I-Type: op Rs Rt Immed 16 Type op funct ADDI xx ADDIU xx SLTI xx SLTIU xx ANDI xx ORI xx XORI xx LUI xx Type op funct ADD ADDU SUB SUBU AND OR XOR NOR Type op funct SLT SLTU funct = m (b3, b2, b1, b0) where b0 tells whether its signed (0) or not (1) (i.e., is overflow activated), b1 tells whether its an add (0) or subtract (1) operation, b2 tells whether it’s a logic operation (1) or arithmetic operation (2), and b3 tells whether its an immediate operation (1) or not (0) (except for slt)

Design Trick: Divide & Conquer
Break the problem into simpler problems, solve them and glue together the solution Example: assume the immediates have been taken care of before the ALU now down to 10 operations can encode in 4 bits 0 add 1 addu 2 sub 3 subu 4 and 5 or 6 xor 7 nor a slt b sltu

Addition & Subtraction
Just like in grade school (carry/borrow 1s) 0101 Two's complement operations are easy do subtraction by negating and then adding > > + 1010 Overflow (result too large for finite computer word) e.g., adding two n-bit numbers does not yield an n-bit number 0001 for lecture 1000

Building a 1-bit Binary Adder
carry_in A B carry_in carry_out S 1 A 1 bit Full Adder S B carry_out S = A xor B xor carry_in carry_out = A&B | A&carry_in | B&carry_in (majority function) How can we use it to build a 32-bit adder? How can we modify it easily to build an adder/subtractor?

Building 32-bit Adder 1-bit FA A0 B0 S0 c0=carry_in c1 Just connect the carry-out of the least significant bit FA to the carry-in of the next least significant bit and connect . . . 1-bit FA A1 B1 S1 c2 1-bit FA A2 B2 S2 c3 Ripple Carry Adder (RCA) advantage: simple logic, so small (low cost) disadvantage: slow and lots of glitching (so lots of energy consumption) c32=carry_out 1-bit FA A31 B31 S31 c31 . . .

A 32-bit Ripple Carry Adder/Subtractor
add/sub 1-bit FA S0 c0=carry_in c1 S1 c2 S2 c3 c32=carry_out S31 c31 . . . A0 A1 A2 A31 Remember 2’s complement is just complement all the bits add a 1 in the least significant bit B0 control (0=add,1=sub) B0 if control = 0 !B0 if control = 1 A > B > + For lecture 1001 1 0001 1 0001

Overflow Detection and Effects
Overflow: the result is too large to represent in the number of bits allocated When adding operands with different signs, overflow cannot occur! Overflow occurs when adding two positives yields a negative or, adding two negatives gives a positive or, subtract a negative from a positive gives a negative or, subtract a positive from a negative gives a positive On overflow, an exception (interrupt) occurs Control jumps to predefined address for exception Interrupted address (address of instruction causing the overflow) is saved for possible resumption Don't always want to detect (interrupt on) overflow Recalled from some earlier slides that the biggest positive number you can represent using 4-bit is 7 and the smallest negative you can represent is negative 8. So any time your addition results in a number bigger than 7 or less than negative 8, you have an overflow. Keep in mind is that whenever you try to add two numbers together that have different signs, that is adding a negative number to a positive number, overflow can NOT occur. Overflow occurs when you to add two positive numbers together and the sum has a negative sign. Or, when you try to add negative numbers together and the sum has a positive sign. If you spend some time, you can convince yourself that If the Carry into the most significant bit is NOT the same as the Carry coming out of the MSB, you have a overflow.

New MIPS Instructions Sign extend – addi, addiu, slti, sltiu
Category Instr Op Code Example Meaning Arithmetic (R & I format) add unsigned 0 and 21 addu $s1, $s2, $s3 $s1 = $s2 + $s3 sub unsigned 0 and 23 subu $s1, $s2, $s3 $s1 = $s2 - $s3 add imm.unsigned 9 addiu $s1, $s2, 6 $s1 = $s2 + 6 Data Transfer ld byte unsigned 24 lbu $s1, 20($s2) $s1 = Mem($s2+20) ld half unsigned 25 lhu $s1, 20($s2) Cond. Branch (I & R format) set on less than unsigned 0 and 2b sltu $s1, $s2, $s3 if ($s2<$s3) $s1=1 else $s1=0 set on less than imm unsigned b sltiu $s1, $s2, 6 if ($s2<6) $s1=1 else similarity of the binary representation of related instructions simplifies the hardware design Sign extend – addi, addiu, slti, sltiu Zero extend – andi, ori, xori Overflow detected – add, addi, sub

Minimal Implementation of a Full Adder
Gate library: inverters, 2-input nands, or-and-inverters architecture concurrent_behavior of full_adder is signal t1, t2, t3, t4, t5: std_logic; begin t1 <= not A after 1 ns; t2 <= not cin after 1 ns; t4 <= not((A or cin) and B) after 2 ns; t3 <= not((t1 or t2) and (A or cin)) after 2 ns; t5 <= t3 nand B after 2 ns; S <= not((B or t3) and t5) after 2 ns; cout <= not(t1 or t2) and t4) after 2 ns; end concurrent_behavior; Can you create the equivalent schematic? Can you determine worst case delay (the worst case timing path through the circuit)?

Tailoring the ALU to the MIPS ISA
Also need to support the logic operations (and,nor,or,xor) Bit wise operations (no carry operation involved) Need a logic gate for each function and a mux to choose the output Also need to support the set-on-less-than instruction (slt) Uses subtraction to determine if (a – b) < 0 (implies a < b) Also need to support test for equality (bne, beq) Again use subtraction: (a - b) = 0 implies a = b Also need to add overflow detection hardware overflow detection enabled only for add, addi, sub Immediates are sign extended outside the ALU with wiring (i.e., no logic needed)

A Simple ALU Cell with Logic Op Support
B add/subt 1-bit FA carry_in carry_out result op Old book shows the B input to the logic gates as the output of the inverter mux (xor in our case) . This way you can also get A and !B, A or !B, A xor !B (which is A xnor B) and !(A or !B) (which is !A and B) in addition to A and B, A or B, A xor B, and A nor B by setting the add/subt control correctly. wouldn’t it be better to pull it directly from the B input? Yes, so I modified the design from that presented in the (old) book. Leads to simplier decoding of m bits (to ALUlogic) to the add_subt and op control lines. how many bits does op need to be?

Modifying the ALU Cell for slt
add/subt carry_in op A 1 2 result 3 1-bit FA 6 B less 7 add/subt carry_out

Modifying the ALU for slt
B1 A0 B0 A31 B31 + result1 less result0 result31 First perform a subtraction Make the result 1 if the subtraction yields a negative result Make the result 0 if the subtraction yields a positive result set tie the most significant sum bit (sign bit) to the low order less input For lecture

Modifying the ALU for Zero
op add/subt Modifying the ALU for Zero A0 First perform subtraction Insert additional logic to detect when all result bits are zero result0 zero . . . B0 + less A1 result1 B1 + less For lecture A31 result31 Note zero is a 1 when result is all zeros B31 + less set

Overflow Detection Overflow occurs when the result is too large to represent in the number of bits allocated adding two positives yields a negative or, adding two negatives gives a positive or, subtract a negative from a positive gives a negative or, subtract a positive from a negative gives a positive On your own: Prove you can detect overflow by: Carry into MSB xor Carry out of MSB For lecture Recalled from some earlier slides that the biggest positive number you can represent using 4-bit is 7 and the smallest negative you can represent is negative 8. So any time your addition results in a number bigger than 7 or less than negative 8, you have an overflow. Keep in mind is that whenever you try to add two numbers together that have different signs, that is adding a negative number to a positive number, overflow can NOT occur. Overflow occurs when you to add two positive numbers together and the sum has a negative sign. Or, when you try to add negative numbers together and the sum has a positive sign. If you spend some time, you can convince yourself that If the Carry into the most significant bit is NOT the same as the Carry coming out of the MSB, you have a overflow. 1 1 1 1 1 1 1 + 7 3 1 + –4 – 5 – 6 1 1 7

Modifying the ALU for Overflow
op add/subt Modifying the ALU for Overflow A0 Modify the most significant cell to determine overflow output setting Enable overflow bit setting for signed arithmetic (add, addi, sub) result0 B0 + less A1 result1 B1 + . . . zero less For slt (and slti and sltiu and sltu) “No integer overflow exception occurs under any circumstances. The comparison is valid even if the subtraction used during the comparison overflows.” The way I read this is that if the result overflows during the subtraction, no attempt is made to correct the set line to reflect that! Otherwise, you would need to add additional logic in front of the set line to do the correction in case of overflow. Like exoring the overflow bit with the sign bit. A31 result31 overflow + B31 less set

But What about Performance?
Critical path of n-bit ripple-carry adder is n*CP Design trick – throw hardware at it (Carry Lookahead) CarryIn0 A0 1-bit ALU Result0 B0 CarryOut0 CarryIn1 A1 1-bit ALU Result1 B1 CarryOut1 CarryIn2 A2 1-bit ALU Result2 B2 CarryOut2 CarryIn3 A3 1-bit ALU Result3 B3 CarryOut3

More complicated than addition
Multiplication More complicated than addition Can be accomplished via shifting and adding (multiplicand) x_ (multiplier) (partial product array) (product) Double precision product produced More time and more area to compute

Add and Right Shift Multiplier Hardware
= 6 multiplicand add 32-bit ALU shift right product multiplier Control = 5 add For lecture add add add = 30

MIPS Multiply Instruction
Multiply (mult and multu) produces a double precision product mult $s0, $s1 # hi||lo = $s0 * $s1 Low-order word of the product is left in processor register lo and the high-order word is left in register hi Instructions mfhi rd and mflo rd are provided to move the product to (user accessible) registers in the register file x18 multu – does multiply unsigned Both multiplies ignore overflow, so its up to the software to check to see if the product is too big to fit into 32 bits. There is no overflow if hi is 0 for multu or the replicated sign of lo for mult. Multiplies are usually done by fast, dedicated hardware and are much more complex (and slower) than adders

Division Division is just a bunch of quotient digit guesses and left shifts and subtracts n n quotient dividend divisor partial remainder array remainder n

MIPS Divide Instruction
Divide generates the reminder in hi and the quotient in lo div $s0, $s1 # lo = $s0 / $s1 # hi = $s0 mod $s1 Instructions mflo rd and mfhi rd are provided to move the quotient and reminder to (user accessible) registers in the register file op rs rt rd shamt funct Seems odd to me that the machine doesn’t support a double precision dividend in hi || lo but it looks like it doesn’t As with multiply, divide ignores overflow so software must determine if the quotient is too large. Software must also check the divisor to avoid division by 0.

Shift Operations Shifts move all the bits in a word left or right
sll $t2, $s0, 8 #$t2 = $s0 << 8 bits srl $t2, $s0, 8 #$t2 = $s0 >> 8 bits sra $t2, $s0, 8 #$t2 = $s0 >> 8 bits op rs rt rd shamt funct Notice that a 5-bit shamt field is enough to shift a 32-bit value 25 – 1 or 31 bit positions Logical shifts fill with zeros, arithmetic left shifts fill with the sign bit An arithmetic shift (sra) maintain the arithmetic correctness of the shifted value (i.e., a number shifted right one bit should be ½ of its original value; a number shifted left should be 2 times its original value) The shift operation is implemented by hardware separate from the ALU using a barrel shifter (which would takes lots of gates in discrete logic, but is pretty easy to implement in VLSI)

Parallel Programmable Shifters
Shift amount (Sh4Sh3Sh2Sh1Sh0) Shift direction (left, right) Shift type (logical, arithmetic) = Control Data Out Data In Shifting a data word left or right over a constant amount is a trivial hardware operation and is implemented by the appropriate signal wiring

Logarithmic Shifter Structure
shifts of 0 or 1 bits !Sh0 Sh0 0,1 shifts shifts of 0 or 16 bits !Sh4 Sh4 0,1,2…31 shifts shifts of 0 or 8 bits !Sh3 Sh3 0,1,2…15 shifts shifts of 0 or 4 bits !Sh2 Sh2 0,1,2,3,4,5,6,7 shifts shifts of 0 or 2 bits !Sh1 Sh1 0,1,2,3 shifts Sh1 & right dataini dataouti dataini-2 dataini+2 Sh1 & left !Sh0 Sh0 & right dataini dataouti dataini-1 dataini+1 Sh0 & left !Sh0 Data Out Data In For lecture

Representing Big (and Small) Numbers
What if we want to encode the approx. age of the earth? 4,600,000, or x 109 or the weight in kg of one a.m.u. (atomic mass unit) or x 10-27 There is no way we can encode either of the above in a 32-bit integer. Floating point representation (-1)sign x F x 2E Still have to fit everything in 32 bits (single precision) Notice that in scientific notation the mantissa is represented in normalized form (no leading zeros) s E (exponent) F (fraction) 1 bit bits bits The base (2, not 10) is hardwired in the design of the FPALU More bits in the fraction (F) or the exponent (E) is a trade-off between precision (accuracy of the number) and range (size of the number)

Exception Events in Floating Point
Overflow (floating point) happens when a positive exponent becomes too large to fit in the exponent field Underflow (floating point) happens when a negative exponent becomes too large to fit in the exponent field One way to reduce the chance of underflow or overflow is to offer another format that has a larger exponent field Double precision – takes two MIPS words s E (exponent) F (fraction) 1 bit bits bits F (fraction continued) 32 bits

IEEE 754 FP Standard Most (all?) computers these days conform to the IEEE 754 floating point standard (-1)sign x (1+F) x 2E-bias Formats for both single and double precision F is stored in normalized format where the msb in F is 1 (so there is no need to store it!) – called the hidden bit To simplify sorting FP numbers, E comes before F in the word and E is represented in excess (biased) notation where the bias is -127 (-1023 for double precision) so the most negative is = = and the most positive is = = 2+127 Examples (in normalized format) Smallest+: = 1 x Zero: = true 0 Largest+: = x 1.02 x 2-1 = x 24 = Book distinguishes between the representation with the hidden bit there – significand (the 24 bit version) , and the one with the hidden bit removed – fraction (the 23 bit version) .75 = 0.11 base 2 = 1.1 and decrement the exponent base 2 Excess exponents ( ) reserved for true zero (with F=0) or denorms (with F != 0) so -126 so -125 … so -2 so -1 so 0 (e.g., so can represent 1 x 2^0 ) so +1 so +2 so +3 so +127 so +128, but reserved for infinity with F = 0 and NAN with F != 0

Wrap-Up We can build an ALU to support the MIPS ISA
we can efficiently perform subtraction using two’s complement we can replicate a 1-bit ALU to produce a 32-bit ALU Important points about hardware all of the gates are always working (concurrent) the speed of a gate is affected by the number of inputs to the gate (fan-in) and the number of gates that the output is connected to (fan-out) the speed of a circuit is affected by the speed of and number of gates in series (on the “critical path” or the “number of levels of logic”) and the length of wires interconnecting the gates Our primary focus is comprehension, however, clever changes to organization can improve performance (similar to using better algorithms in software)

XU, Qiang 徐強 [Adapted from UC Berkeley’s D. Patterson’s and

Similar presentations

Presentation on theme: "XU, Qiang 徐強 [Adapted from UC Berkeley’s D. Patterson’s and"— Presentation transcript:

Similar presentations

About project

Feedback

Log in

Auth with social network:

XU, Qiang 徐強 [Adapted from UC Berkeley’s D. Patterson’s and

Similar presentations

Presentation on theme: "XU, Qiang 徐強 [Adapted from UC Berkeley’s D. Patterson’s and"— Presentation transcript:

Similar presentations

About project

Feedback