1. Hardware Testing and Designing for Testability
RTLAB
최치호

2. Contents TESTING COMBINATIONAL LOGIC TESTING SEQUENTIAL LOGIC
SCAN TESTING
BOUNDARY SCAN
BUILT-IN SELF-TEST

3. TESTING COMBINATIONAL LOGIC
Fault Type
Stuck-at-Faults
. Stuck-at-0
. Stuck-at-1
2. Bridging Faults
. Two unconnected signal
lines are shorted together

4. Testing an AND-OR Network

5. Example Network for Stuck-at Fault Testing

6. TESTING SEQUENTIAL LOGIC
More difficult than testing combinational logic
Use sequences of inputs for testing
Way to derive test sequences
Iterative Network
Based on testing for stuck-at faults

7. Sequential and Iterative Networks

8. Based on testing for stuck-at faults

9. SCAN TESTING
Scan Path Test Circuit Using Two-port Flip-flops

10. System with Flip-flop Registers and Combinational Logic Blocks

11. BOUNDARY SCAN
TAP Test access port

12. Typical Boundary Scan Cell

13. Basic Boundary Scan Architecture
- BSR (Boundary Scan Register)

14. BUILT-IN SELF-TEST Digital systems become more and more complex
Add logic to the IC so that it can test itself
=> Built-In Self-Test (BIST)
Generic BIST Scheme

15. Self-test Circuit for RAM with Signature Register
Signature register : compress the output data into a short string of bits called a signature
MISR : Multiple-Input Signature Register

16. Modified LFSR with 0000 State
4-bit Linear Feedback Shift Register (LFSR)
Multiple-input Signature Register (MISR)
Pattern generated are:
1000,1100,1110,1111,0111,1011,
0101,1010,1101,0110,0011,1001,
0100,0010,0001,1000,….

17. BIST Using BILBO (Built-in logic block observation) Register
PRPG : Pseudo random pattern generator, LFSR

18. 4-bit BILBO Register
(MIST)

19. VHDL Code for BILBO Register
-- NBITS : The number of bits