1. SUBJECT:COMPUTER ORGANISATION SUBJECT CODE:2140707 B.E. 4th SEMESTER
GUIDED BY
PROF.BHUMIKA BHATT
PROF.MEHUL KHATIWALA

2. CONTRIBUTORS SNEHA GANGWANI(130420107022) KHUSHBOO GOHEL(130420107023)
HARSH GANDHI( )
HIREN CHAUDHRY( )
JAY DHANANI( )

3. Central Processing Unit
Introduction
General register organisation
Stack organisation
Instruction format
Addressing modes
Data transfer and manipulation
Program control
RISC(Reduced Instruction Set Computer)
Topic:central processing unit

4. MAJOR COMPONENTS OF CPU
Storage Components
Registers
Flags
Execution (Processing) Components
Arithmetic Logic Unit(ALU)
Arithmetic calculations, Logical computations, Shifts/Rotates
Transfer Components
Bus
Control Components
Control Unit
Register
File
ALU
Control Unit

5. REGISTERS
In Basic Computer, there is only one general purpose register, the Accumulator (AC)
In modern CPUs, there are many general purpose registers
It is advantageous to have many registers
Transfer between registers within the processor are relatively fast
Going “off the processor” to access memory is much slower

6. GENERAL REGISTER ORGANIZATION
BUS: A, B
MUX
SELA { }
SELB
ALU
OPR R1 R2 R3 R4 R5 R6 R7
Input
3 x 8
decoder
SELD
Load
(7 lines)
Output
A bus
B bus
Clock
(7 lines)

7. OPERATION OF CONTROL UNIT
The control unit
Directs the information flow through ALU by
- Selecting various Components in the system
- Selecting the Function of ALU
Example: R1  R2 + R3
[1] MUX A selector (SELA): BUS A  R2
[2] MUX B selector (SELB): BUS B  R3
[3] ALU operation selector (OPR): ALU to ADD
[4] Decoder destination selector (SELD): R1  Out Bus
SELA
SELB
SELD
OPR 3 5
Control Word
Encoding of register selection fields
Binary
Code SELA SELB SELD
000 Input Input None
001 R1 R1 R1
010 R2 R2 R2
011 R3 R3 R3
100 R4 R4 R4
101 R5 R5 R5
110 R6 R6 R6
111 R7 R7 R7

8. ALU CONTROL Encoding of ALU operations Examples of ALU Microoperations
OPR
Select Operation Symbol
00000 Transfer A TSFA
00001 Increment A INCA
00010 ADD A + B ADD
00101 Subtract A - B SUB
00110 Decrement A DECA
01000 AND A and B AND
01010 OR A and B OR
01100 XOR A and B XOR
01110 Complement A COMA
10000 Shift right A SHRA
11000 Shift left A SHLA
Examples of ALU Microoperations
Symbolic Designation
Microoperation SELA SELB SELD OPR Control Word
R1  R2  R R R3 R SUB
R4  R4  R R R5 R OR
R6  R R R INCA
R7  R R R TSFA
Output  R R None TSFA
Output  Input Input None TSFA
R4  shl R R R SHLA
R5  R R5 R XOR

9. REGISTER STACK ORGANIZATION
- Very useful feature for nested subroutines, nested interrupt services
- Also efficient for arithmetic expression evaluation
- Storage which can be accessed in LIFO
- Pointer: SP OR POS
- Only PUSH and POP operations are applicable
stack
Address
Register Stack
Flags 63
FULL
EMPTY
Stack pointer 4 SP C 3
6 bits B 2 A 1
Push, Pop operations DR
/* Initially, SP = 0, EMPTY = 1, FULL = 0 */
PUSH
POP
SP  SP DR  M[SP]
M[SP]  DR SP  SP  1
If (SP = 0) then (FULL  1) If (SP = 0) then (EMPTY  1)
EMPTY  FULL  0

10. MEMORY STACK ORGANIZATION
1000
Memory with Program, Data,
and Stack Segments
Program PC
(instructions)
Data AR
(operands)
3000 SP
stack
3997
3998
3999
4000
4001
- A portion of memory is used as a stack with a
processor register as a stack pointer
- PUSH: SP  SP - 1
M[SP]  DR
- POP: DR  M[SP]
SP  SP + 1
Stack grows
In this direction
- Most computers do not provide hardware to check stack overflow (full
stack) or underflow (empty stack)  must be done in software

11. REVERSE POLISH NOTATION
Arithmetic Expressions: A + B
A + B Infix notation
+ A B Prefix or Polish notation
A B + Postfix or reverse Polish notation
- The reverse Polish notation is very suitable for stack manipulation
Evaluation of Arithmetic Expressions
Any arithmetic expression can be expressed in parenthesis-free
Polish notation, including reverse Polish notation
(3 * 4) + (5 * 6)  * 5 6 * + 6 4 5 5 30 3 3 12 12 12 12 42 3 4 * 5 6 * +

12. Three-Address Instructions
Computers with three-address instruction formats can use each address field to specify either a processor register or a memory operand.
The program in assembly language that evaluates X=(A+B)*(C+D) is shown below, together with comments that explain the register transfer operation of each instruction.

13. The advantage of three-address is that it results in short programs when evaluation arithmetic expressions.
The disadvantage is that the binary-coded instructions require too many bits to specify three- address.
An example of a commercial computer that uses three-address instruction is the Cyber 170.

14. Two-Address Instruction
Two-address instructions are the most common in commercial computers. The program to evaluate X=(A+B)*(C+D) is as follows :
The MOV instruction moves or transfers the operands to and from memory and processor registers. The first symbol listed in an instruction is assumed to be both a source and the destination where the result of the operation is transferred.

15. One-Address Instruction
One-Address Instruction use an implied accumulator (A) register for all data manipulation. For manipulation and division there is a need for a second register.
The program to evaluate X+(A+B)*(C+D) is
ALL operations are done between the AC register and a memory operand. T is the address of a temporary memory location required for storing the intermediate result.

16. Zero-Address Instruction
A tack-organized computer does not use an address field for the instructions ADD and MUL. The PUSH and POP instructions, however, need an address field to specify the operand that communicates with the stack.
The following program shows how X=(A+B)*(C+D) will be written for a stack-organized computer.

17. To evaluate arithmetic expressions in stack computer, it is necessary to convert the expression into reverse Polish notation.
The name “zero-address” is given to this type of computer because of the absence of an address field in the computational instructions.

18. ADDRESSING MODES
Implied Mode :In this mode the operands are specified implicitly in the definition of the instruction. For example, the instruction “complement accumulator” is an implied mode instruction because the operand in the accumulator register is implied in the definition of the instruction.
Immediate Mode: In this mode the operand is specified in the instruction itself. In other words, an immediate mode instruction has an operand field rather than the address field. Immediate mode instruction are useful for initializing registers to a constant value. 18

19. 3) Register Mode : In this mode the operands are in registers that reside within the CPU. The particular register is selected from a register field in the instruction.
MOV R1,R2
4) Register Indirect Mode : In this mode the instruction specifies a register in the CPU whose contents give the address of the operand I in memory . In other words, the selected register contains the address of the operand rather than the operand itself.
5) Autoincrement and Autodecrement Mode: This is similar to the register in direct mode except that the register is incremented or decremented after its value is used to access memory.

20. 6) Direct Address Mode : In this mode the effective address is equal to the address part of the instruction. The operand is resides in the memory and its address is given directly by the address field of the instruction.
7) Indirect Address Mode : In this mode the address field of the instruction gives the address of the effective address is stored in the memory. Control fethes the instruction from memory and uses its address part to access memory again to read the effective address.
Effective address= address part of the instruction +content of CPU register.

21. 8) Relative Address Mode: In this mode the content of the program counter is added to the address part of the instruction in order to obtain the effective address
9) Indexed Addressing Mode :In this mode the content of an index register is added to the part of the instruction to obtain the effective address. Index register is the special CPU register that contains an index value. The address field of the instruction defines the beginning address of a data array in the memory.
10) Base Register Addressing Mode: In this mode the content of the base register is added to the address part of the instruction to obtain the effective address. This is similar to the indexed addressing mode except that the register is now called the base register instead of an index register.

22. Data Transfer instructions
Most computer instructions can be classified into three categories:
1) Data transfer
2) Data manipulation
3) Program control instructions

23. Addressing modes
Data Transfer Instructions with Different Addressing Modes
Assembly
Convention
Mode
Register Transfer
Direct address LD ADR AC M[ADR]
Indirect address LD @ADR AC  M[M[ADR]]
Relative address LD $ADR AC  M[PC + ADR]
Immediate operand LD #NBR AC  NBR
Index addressing LD ADR(X) AC  M[ADR + XR]
Register LD R1 AC  R1
Register indirect LD (R1) AC  M[R1]
Autoincrement LD (R1)+ AC  M[R1], R1  R1 + 1
Autodecrement LD -(R1) R1  R1 - 1, AC  M[R1]

24. Typical Data Transfer Instruction:
Load : transfer from memory to a processor register, usually an AC (memory read)
Store : transfer from a processor register into memory (memory write)
Move : transfer from one register to another register
Exchange : swap information between two registers or a register and a memory word
Input / Output : transfer data among processor registers and input/output device
Push/Pop : transfer data between processor registers and a memory stack

25. Overview Typical Data Transfer Instructions Name Mnemonic Load LD
Store ST
Move MOV
Exchange XCH
Input IN
Output OUT
Push PUSH
Pop POP 25

26. Program control Program Control Instruction:
Branch and Jump instructions are used interchangeably to mean the same thing
NAME
MNEMONIC
BRANCH BR
JUMP
JMP
SKIP
SKP
CALL
RETURN
RET
COMPARE (BY SUBTRACTION)
CMP
TEST (BY ENDING)
TST

27. Status Bit Conditions:
Condition Code Bit or Flag Bit
The bits are set or cleared as a result of an operation performed in the ALU
Arithmetic Instructions
Shift Instructions
Name Mnemonic
Logical shift right SHR
Logical shift left SHL
Arithmetic shift right SHRA
Arithmetic shift left SHLA
Rotate right ROR
Rotate left ROL
Rotate right thru carry RORC
Rotate left thru carry ROLC
Name Mnemonic
Increment INC
Decrement DEC
Add ADD
Subtract SUB
Multiply MUL
Divide DIV
Add with Carry ADDC
Subtract with Borrow SUBB
Negate(2’s Complement) NEG
Name Mnemonic
Clear CLR
Complement COM
AND AND
OR OR
Exclusive-OR XOR
Clear carry CLRC
Set carry SETC
Complement carry COMC
Enable interrupt EI
Disable interrupt DI
Logical and Bit Manipulation Instructions

29. Subroutine Call and Return
CALL: SP<-SP-1 //decrement stack point
M[SP]<-PC //push content of pc onto stack
PC<-effective address //transfer control to subroutine
RETURN: PC<-M[SP]//pop stack &trabsfer to pc
SP<-SP+1//increment stack pointer

30. Typical set of branch instruction
MNEMOIC
CONDITION
EXPLANATION
BEQ ==
Branch if equal
BNE !=
Branch if not equal
BGT
>
Branch if greater than
BLT
<
Branch if less than
BGE
>=
Branch if greater or equal
BLE
<=
Branch if less than or equal
BRA
Branch always (unconditional)

31. BHI
UNSIGNED >
Branch if higher
BLO
UNSIGNED <
Branch if lower
BHS
UNSIGNED >=
Branch if higher or same
BLS
UNSIGNED <=
Branch if lower or same
BCS
Branch if carry set
BCC
Branch if carry clear
BVS
Branch if overflow set
BVC
Branch if overflow clear
BPL
>=0
Branch if ‘plus’
BMI
<0
Branch if ‘minus’

32. Program interrupt
Transfer program control from a currently running program to another service program as a result of an external or internal generated request
Control returns to the original program after the service program is executed.

33. Interrupt Service Program
Subroutine Call
An interrupt is initiated by an internal or external signal (except for software interrupt) n A subroutine call is initiated from the execution of an instruction (CALL)
The address of the interrupt service program is determined by the hardware n The address of the subroutine call is determined from the address field of an instruction
An interrupt procedure stores all the information necessary to define the state of the CPU n A subroutine call stores only the program counter (Return address)

34. Program Status Word (PSW)
The collection of all status bit conditions in the CPU
Two CPU Operating Modes
Supervisor (System) Mode : Privileged Instruction
When the CPU is executing a program that is part of the operating system

35. Types of Interrupts External Interrupts
come from I/O device, from a timing device, from a circuit monitoring the power supply, or from any other external source
Internal Interrupts or TRAP
caused by register overflow, attempt to divide by zero, an invalid operation code, stack overflow, and protection violation
Software Interrupts
initiated by executing an instruction (INT or RST)
used by the programmer to initiate an interrupt procedure at any desired point in the program

36. Control Unit
A control unit is circuitry that directs operations within a computer's processor. It lets the computer's logic unit, memory, as well as both input and output devices know how to respond to instructions received from a program. Examples of devices that utilize control units include CPUs and GPUs.

37. A control unit works by receiving input information that it converts into control signals, which are then sent to the central processor. The computer's processor then tells the attached hardware what operations carry out. The functions a control unit performs depend on the type of CPU, due to the variance of architecture between different manufacturers. The following diagram illustrates how instructions from a program are processed.

39. Reduced Instruction Set Computer (RISC)
Complex Instruction Set Computer (CISC)
Major characteristics of a CISC architecture
1) A large number of instructions -typically from 100 to 250 instruction.
2) Some instructions that perform specialized tasks and are used infrequently.
3) A large variety of addressing modes -typically from 5 to 20 different modes.
4) Variable-length instruction formats.
5) Instructions that manipulate operands in memory.

40. Reduced Instruction Set Computer (RISC)
Major characteristics of a RISC architecture
1) Relatively few instructions.
2) Relatively few addressing modes.
3) Memory access limited to load and store instruction.
4) All operations done within the registers of the CPU.
5) Fixed-length, easily decoded instruction format.
6) Single-cycle instruction execution.
7) Hardwired rather than micro programmed control.

41. Other characteristics of a RISC architecture
1) A relatively large number of registers in the processor unit.
2) Use of overlapped register windows to speed-up procedure call and return
3) Efficient instruction pipeline.
4) Compiler support for efficient translation of high-level language programs into machine language programs.
Overlapped Register Windows
Time consuming operations during procedure call
Saving and restoring registers.
Passing of parameters and result.
Provide the passing of parameters and avoid the need for saving and restoring register values by hardware.

42. Concept of overlapped register windows :
Total 74 registers : R0 -R73
R0 -R9 : Global registers
R10 -R63 : 4 windows
Window A ,Window B, Window C, WindowD.
in this 4 sets of window
there are 10 locals registers + 2 sets of 6 registers.
(Example)Procedure A calls procedure B
R26 -R31
Store parameters for procedure B
Store results of procedure B
R16 -R25 : Local to procedure A
R32 -R41 : Local to procedure B
Window Size = L + 2C + G = 10 + ( 2 X 6 ) + 10 = 32 registers
Register File (total register) = (L + C) X W + G = ( ) X = 74 registers
G: Global registers = 10
L: Local registers = 10
C: Common registers = 6
W: Number of windows = 4