1. R. Piandani2 , F. Spinella2, M.Sozzi1 , S. Venditti 3
The TEL62: a Real-Time board for the NA62 Trigger and Data Acquisition. Data Flow and Firmware Design
B. Angelucci1,2, G.Lamanna2, M.Minuti2, E. Pedreschi1,2, J. Pinzino1,2 ,
R. Piandani2 , F. Spinella2, M.Sozzi1 , S. Venditti 3
( 1 University of Pisa, 2 INFN sez. Pisa, 3 CERN Geneva)
NA62 experiment
The NA62 detectors
NA62 aims at measuring K+→π+νν with O(100) SM events, in two years of data taking. This is an unique and extremely accurate process and a clean probe for the non-trivial flavour structure of physics beyond the Standard Model
Very challenging experiment. With stringent requirements:
400 GeV SPS Proton beam π ν
~10MHz
~800MHz
~50MHz
75(±1%) Gev/c
~6% K
The K+ component in the beam is identified by a differential Čerenkov (CEDAR) counter
The coordinates and momentum of individual beam particles are registered before entering the decay region by 3 silicon pixel tracking detectors (GTK)
Guard-ring counters (CHANTI) surrounding the last GTK station veto charged particles upstream of the decay region
A magnetic spectrometer (STRAW tubes Tracker) measures the coordinates and momentum of charged particles originating from the decay region.
A Čerenkov counter (RICH) counter identifies pions with respect to muons
A set of photon-veto detectors provides coverage from zero out to ~50mr angles from the decay region. This is assured by the high-resolution e.m. (LKR) calorimeter, by a set of small-angle calorimeters (SAC) and, at large angles, by a series of annular photon-veto (LAV) detectors.
A muon-veto detector (MUV), composed of a two-part hadron calorimeter followed by additional iron and a transversally-segmented hodoscope
high-resolution timing - to support a high-rate environment
particle identification of kaons, pions, muons, electrons and photons
hermetic vetoing of photons out to large angles and of muons within the acceptance
redundancy of information
The Trigger-DAQ system (TDAQ)
TEL62 architecture
4 Daughter Card (DC):
TEL62 is able to support up to 4 TDCB daughter-cards
most sub-d need TDCs: 1 TDCB = 4 CERN HPTDCs (128 channels) => 512 channels per TEL62
4 PP- FPGAs:
each one connected to one of the daughter cards
DDR2 external buffer memories used for data storage during the L0 trigger latency
SL-FPGA:
Receives L0 primitives from each PPs, merges and send them to Level0 central processor via Quad-GbE mezzanine
Receives and merge data from PPs, performs data reduction
CCPC (CPU):
Embedded Credit card PC handles the TEL62 slow control and configuration (running Linux)
TTC:
standard LHC connection for trigger and clock
Quad GbE:
Standard GBE network card (4 links) allows data collection on PCs
The trigger and DAQ system is based on a common board (TEL62)
Each board provides support both for acquisition and generation of trigger primitives.
Special mezzanines for TEL62 (mainly TDCs) interface with sub-detectors front-ends.
TEL62 provides asynchronous GBE data transmission (4Gb/s) and receives synchronous trigger requests via TTC standard
The maximum trigger rate to the TEL62 is 1 MHz, with a latency of 1 ms
Trigger primitives are received by the L0 processor , L1 and L2 are software based.
PP firmware block diagram
SL firmware block diagram
SPI3TX
SPI3RX
Header mem
TX mem
Data packet sender
TX hdr mem
Header builder
MEP assembler
QDR mux
MEP info FIFO
MEP data FIFO
MEP location mem
Data header FIFO
MEP length FIFO
Evt data FIFO
Evt length FIFO
Event generator
Event generator mem
RX mem
Event merger
PP data FIFO
Test FIFO 1
QDR
TTC handler
Timestamp FIFO
Type FIFO
Trigger dispatcher PP
Data builder
Data distributor
Hdr mem arbiter
Event mux
Check summer
PP-SL tester
Test mem 1
Intlb tester
QPLL monitor
Choke Error
Logger
Log FIFO
SL data FIFO
SL data source
Triginfo FIFO
Trigger generator
QDR interface 2 2 3
Input buffer
Output buffer
DDR writer
DDR
Frame buffers
PP-SL tester
Test mem 1
Logger
Log FIFO
Triginfo RX SL
Data
FIFO
Data organizer
DDR arbiter
Monitoring
DDR reader IB
Data mux
Trigger mux
FB mux
DDR mux
PP-SL transmitter
Trigger generator
Trig
FIFOmux OB
Black box
Data compressor
Hit counters 1 4 1 3
1) Data coming from 4 TDCs are collected and merged
2) Data are organized on the fly in the DDR2 buffer
Each page is related to a well defined 25 ns time slot
Link with DDR2 at 160MHz x 256bit = 41Gb/s
3) A copy of the data flow is used for trigger primitives generation
4) After a L0 request (mean rate 1 MHz) a programmable number of 25 ns slots is extracted from DDR2 and sent to the SL-FPGA
1) TTC interface decodes trigger information and sends it to PP-FPGAs
2) PP data are merged, pre-processed and synchronized
Data formatted in Multi Event Packet are stored into the QDR
3) UDP packets are built and sent through the 4 links of GBE
Performance
TEL62 performance has been measured, both with simulated and real detectors data
The maximum incoming trigger rate to the TEL62 exceeds the design specifications of MHz mean, decreasing with the event size.
The outgoing data flow bandwidth is only limited by the 4 Gbits links (fully covered)
19 th REAL-TIME Conference
May , Nara, Japan