1. GTK-TO readout interface status
GTK prototype readout interface will use a commercial FPGA development board (Stratix III EP3SL150 development board - ALTERA)
Stefano Chiozzi – INFN sez. Ferrara GTK meeting 28/07/2009

2. GTK-TO readout interface status
Stratix III EP3SL150 development board
Programmer ports
HSMC port B
HSMC port A
Gbit Ethernet port
DDR2 slot
Stefano Chiozzi – INFN sez. Ferrara GTK meeting 28/07/2009

3. GTK-TO readout interface status
Stratix III EP3SL150 development board: HSMC interface
HSMC interface (High Speed Mezzanine Card interface)
The board contains two HSMC interfaces called Port A and Port B. These HSMC interfaces support both single-ended and differential signaling (board-to-board connector type SAMTEC ASP ). The HSMC connector has 172 total pins, including 120 signal pins, 39 power pins, and 13 ground pins. The ground pins are located between the two rows of signal and power pins, acting as both shield and reference.
For information about HSMC interface standard refer to:
“ALTERA HSMC SPECIFICATION v 1.7 – june 2009”
Stefano Chiozzi – INFN sez. Ferrara GTK meeting 28/07/2009

4. GTK-TO readout interface status
Stratix III EP3SL150 development board: HSMC interface
Stefano Chiozzi – INFN sez. Ferrara GTK meeting 28/07/2009

5. GTK-TO readout interface status
Stratix III EP3SL150 development board: HSMC interface
Maximum number of I/O signals (per HSMC interface):
BANK1 4 JTAG, 2 SMBUS, 1 cmos CLKIN0, 1 cmos CLKOUT diff XCVR_TX, 8 diff XCVR_RX
BANK2 D(39:0) cmos -or- D(3:0) cmos + 9 LVDS TX + 9 LVDS RX (including LVDS CLKIN1, LVDS CLKOUT1)
BANK3 D(79:40) cmos -or- 10 LVDS TX + 10 LVDS RX (including LVDS CLKIN2, LVDS CLKOUT2)
NOTES (Stratix III development board):
BANK1 differential lines (reserved for gigabit serial links) are not connected
BANK2 and BANK3 are fully connected to FPGA
Stefano Chiozzi – INFN sez. Ferrara GTK meeting 28/07/2009

6. GTK-TO readout interface status
Stratix III EP3SL150 development board: HSMC interface
HSMC total number of LVDS resources:
BANK2 9 LVDS TX LVDS RX BANK3 10 LVDS TX + 10 LVDS RX
Total: 17 LVDS TX + 17 LVDS RX + 2 LVDS CLKIN + 2 LVDS CLKOUT
NOTES (Stratix III board):
LVDS CLKIN1 cannot be routed to a FPGA-PLL: LVDS CLKIN2 is the true main clock input
CMOS CLKIN0 cannot be routed to a FPGA-PLL (CLKIN0 connected to FPGA generic I/O pin)
Stefano Chiozzi – INFN sez. Ferrara GTK meeting 28/07/2009

7. GTK-TO readout interface status
Stratix III EP3SL150 development board: HSMC interface
GTK-TO interface needs 20 FPGA LVDS RX lines and 10 LVDS TX lines mapped to a single HSMC connector
but
this request is not supported by HSMC base specification (20 LVDS RX needed .vs. 19 LVDS RX standard).
Fortunately, Stratix III board has some FPGA true LVDS inputs connected to single ended signals on HSMC Port B: these resources can be used as additional differential lines so GTK-TO interface connects only to port B without extra wires to port A.
Stefano Chiozzi – INFN sez. Ferrara GTK meeting 28/07/2009

8. GTK-TO readout interface status
Stratix III EP3SL150 development board: HSMC Port B
HSMB pin HSMB FPGA pin FPGA function FPGA I/O
44 D3 AF31 DIFFIO_RX_L36p 2A
43 D2 AF32 DIFFIO_RX_L36n 2A
NOTE: pcb routing for these lines is not perfectly balanced (lines are not designed as differential pair from FPGA to PortB; lines start in pair from FPGA pins, then there is a little area - 40mm x 20mm - before HSMC connector where distance between lines grows; the total distance FPGA-HSMB is ~100mm)
Stefano Chiozzi – INFN sez. Ferrara GTK meeting 28/07/2009

9. GTK-TO readout interface status
Stratix III EP3SL150 development board: HSMC Port B
HSMC Port B LVDS resources controlled by FPGA I/O Bank 2,5,6 (row banks with dedicated LVDS pins)
All LVDS RX lines use FPGA internal 100ohm line termination (pcb-board does not have additional R-term sockets)
GTK-TO interface does not use all LVDS TX lines: spares lines can be configured as differential outputs and/or as single ended I/O for extra control signals.
Mezzanine board should connect HSMB.TDI to HSMB.TDO if JTAG compatible devices are not used
Mezzanine board should also connect HSMB.PSNTn to GND
Stefano Chiozzi – INFN sez. Ferrara GTK meeting 28/07/2009

10. GTK-TO readout interface status
Order tracking: Stratix III EP3SL150 development board
- 3 Stratix III development kits in order (june 2009)
- First dev-kit received on 24/07/2009
- Delivery of remaining items will be scheduled on 06/08/2009
Order tracking: Clock board CDCE62005EVM
- 6 Clock board CDCE62005EVM in order (june 2009)
- 2 Clock board received on 24/07/2009
- remaining items will be scheduled on ?? (waiting for next delivery date from distributor)
Stefano Chiozzi – INFN sez. Ferrara GTK meeting 28/07/2009