1. ECE 551: Digital System Design & Synthesis
Lecture Set 12
12.1: Introduction to VHDL
(Separate File)
12.2: VHDL versus Verilog
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2. Overview Background Comparison Space
ECE Digital System Design & Synthesis Lecture VHDL versus Verilog
Overview
Background
Comparison Space
Capability
Compilation
Data Types
Design Reuse
Ease of Learning
Error- Checking
Forward and Backward Annotation
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3. Overview Comparison Space (Continued) High-Level Constructs
ECE551 - Digital System Design & Synthesis Lecture VHDL versus Verilog
Overview
Comparison Space (Continued)
High-Level Constructs
Language Extensions
Libraries
Low-Level Constructs
Managing Large Designs
Operators
Parameterized Models
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4. Overview Comparison Space (Continued) Comparison Summary
ECE Digital System Design & Synthesis Lecture VHDL versus Verilog
Overview
Comparison Space (Continued)
Procedures and Tasks
Readability
Structural Replication
Testbenches
Verboseness
Comparison Summary
Algorithmic and RTL Level Examples
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5. Background
VHDL (VHSIC Hardware Description Language) VHSIC (Very High Speed Integrated Circuit)
Developed under US military contract
Based on Ada
IEEE Standard 1076 (1987)
IEEE Standard 1076 (1993)
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6. Background Verilog Developed by Gateway Design Automation in 1983
Based on C and Ada
Originally an interpretive language
Gateway bought by Cadence in 1989
Put in public domain in 1990
IEEE Standard
IEEE Standard
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7. Capability - Tie VHDL VITAL Models needed at gate level
Better at abstract modeling
Verilog
May require use of PLI for modeling abstract hardware
Has built-in gate models
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8. Compilation - VHDL + VHDL
Separate compilation of multiple design units in the same file available
Should probably keep each design unit in separate file (tedious in some cases!)
Verilog
Compilation can be dependent on order of code in files and on compilation order of multiple files
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9. Data Types - Verilog + VHDL Verilog
Many language and user-defined data types
Strong type checking
Dedicated conversion functions needed to integrate types in design
Helps to prevent errors
Creates major headache for hardware modeling
Verilog
Data types simple and focused on hardware modeling
Weak type checking
No user-defined data types
Register type confusing - became variable type in 2001 standard
Overall Simple
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10. Design Reuse - VHDL + VHDL
Packages available for sharing functions, procedures, types, and components
Verilog
Functions and procedures must be within same module, or
In separate system file with ‘include compiler directive for use.
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11. Ease of Learning - Verilog +
VHDL
Less intuitive for novice due to strong typing
Many ways to model the same circuit
Verilog
Easiest to grasp and understand for novice
Compiler directive language and PLI add complexity
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12. Error-Checking - VHDL +
Strong typing and bit width consistency permits more checks
Verilog
Weak typing and mixed bit width can be more error-prone and not caught by checks
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13. Forward and Backward Annotation - Tie
VHDL
SDF can be used with VHDL in many commercial simulation products
Verilog
Origin of Standard Delay Format (SDF) for forward- and back-annotating delays
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14. High-Level Constructs - VHDL +
Packages for reuse
Configuration statements for choosing entities and architectures
Generate statements for replicating structure
Generics for parameterizing models
Verilog
Parameterization of models via overload
Configurations added in 2001
Generate statements for replicating structure added in 2001
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15. Language Extensions - Verilog +
VHDL
Attribute ‘foreign allows architectures and subprograms in another language
Verilog
PLI between Verilog and Verilog software tools
Comment:
Use not recommended
But, in captive, non-vendor environment, can be very useful
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16. Libraries - Tie
VHDL
Libraries to store compiled entities, architectures, packages, and configurations
Verilog
Libraries and configurations added in 2001
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17. Low-Level Constructs - Verilog ++
No gate level primitives
Cell primitives defined using VITAL language
Gate level primitives
UDPs and specify blocks for modeling cell primitives for ASICs and PLDs
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18. Managing Large Designs - VHDL +
Packages
Configuration
Generate
Generic
Configurations added in 2001
Generate added in 2001
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19. Operators - Verilog + VHDL Similar to Verilog
Lacking in unary reduction operators (can use loop)
Does not allow concatenate on LHS
Verilog
Similar to VHDL
Allows concatenate on LHS
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20. Parameterized Models - Tie
VHDL
Specific width, delay, etc. model can be instantiated from generic n-bit model using generic statements
Synthesizes only if value of generic given
Verilog
Can be instantiated from a generic fixed bit number model using overload parameter values
Synthesizes without overload uses default values
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21. Procedures and Tasks VHDL Allows concurrent procedure calls Verilog
Allows concurrent task and function calls in 2001
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22. Readability - VHDL + VHDL Verbose (Concise?!) More sentence-like
Verilog
Concise
More cryptic
Bit width mixing confusing and error- prone
Preferred by C programmers, but C + Ada mix may be confusing
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23. Structural Replication - Tie
VHDL
Generate
Verilog
Arrays of instances using concatenation
Generate in 2001
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24. Testbenches - VHDL + VHDL Generics useful
Configuration statements useful
More transparent file handling
Verilog
File handling is hardware like
Configuration statements useful
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25. Verboseness - Verilog ++
VHDL
Requires defined and matching data types
1987 required components
Overall - verbose and often longer code
Verilog
Less explicit type modeling
Overall - less verbose and often much shorter
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26. Comparison Summary By the numbers (no weighting): Verilog VHDL 2 ++ 04 3
By the numbers (no weighting):
VHDL
Tie 3
Verilog 2001 has leveled the playing field!
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27. Comparative Examples Algorithmic Level RTL Level See D. J. Smith paper
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