1. SEEM3460 Tutorial
The Make Utility

2. Basic Structure of A Make File
Line of target and dependency (a rule)
target1: part1.o part2.o #this line and the line below are comments #part1.o and part2.o here are dependents
Lines of operations describing the updating process
[tab]gcc -o target1 part1.o part2.o [tab]chmod 711 target1
The tab character is necessary!

3. Basic Structure of A Make File
Multiple targets can be put in same file:
target1: part1.o part2.o [tab]gcc -o target1 part1.o part2.o part1.o: part1.c part1.h [tab]gcc -c part1.c part2.o: part2.c [tab]gcc -c part2.c

4. Flow of Make Process target1 (8 if 4 or 7): update
part1.o (4): date check (3 if 1 or 2): update
part1.c (1): date check
part1.h (2): date check
part2.o (7): date check (6 if 5): update
part2.c (5): date check

5. The Make Utility Update according to Makefile:
make -f makefile1
Update part1.o according to makefile1:
make -f makefile1 part1.o
Other switches:
-k (continue other targets when a target errs)
-n (do not execute but print the commands)
-s (execute but do not print the commands)

6. Extensive Use of Make Files
The use of a make file is never limited to just compiling a program
Example 1: Update a piece of output output1.txt: input1.txt [tab]program1 < input1.txt > output1.txt
Example 2: Clear temporary files clear: [tab]rm -f tempfile1 tempfile2

7. Macros (Extra)
Macros can be used in make files functioning as variables. The $(marconame) pattern is used to take the value of the macro
E.g. CC = gcc part1.o: part1.c part1.h [tab]$(CC) -c part1.c

8. Special Macros (Extra)
There are some special macros that you can use without defining them
name of target
$?: name of changed dependents
E.g. final: part1.c part2.c [tab]gcc -c $? [tab]gcc -o part1.o part2.o