1. Day 12: October 1, 2012 Variation
ESE370: Circuit-Level Modeling, Design, and Optimization for Digital Systems
Day 12: October 1, 2012
Variation
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2. Previously Understand how to model transistor behavior
Given that we know its parameters
Vdd, Vth, tOX, COX, W, L, NA …
CGC
CGCS
CGCB
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3. But… We don’t know its parameters (perfectly)
Fabrication parameters have error range
Identically drawn devices differ
Parameters change with environment (e.g. Temperature)
Parameters change with time (aging)
Why I am more concerned with robustness than precision.
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4. Today Sources of Variation Coping with Variation Fabrication Operation
Aging
Coping with Variation
Margin
Corners
Binning
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5. Fabrication
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6. Process Shift Oxide thickness Doping level Layer alignment
Growth and Etch rates and times
Depend on chemical concentrations
How precisely can we control those?
Vary machine-to-machine, day-to-day
Impact all transistors on wafer
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7. Systematic Spatial
Parameters change consistently across wafer or chip based on location
Chemical-Mechanical Polishing (CMP)
Dishing
Lens distortion
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8. FPGA Systematic Variation
65nm
Virtex 5
[Tuan et al. / ISQED 2010]
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9. Oxide Thickness [Asenov et al. TRED 2002]
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10. Line Edge Roughness 1.2mm and 2.4mm lines From:
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11. Optical Sources What is the shortest wavelength of visible light?
How compare to 45nm feature size?
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12. Phase Shift Masking Today’s chips use λ=193nm Source
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13. Line Edges (PSM) Source:
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14. Intel 65nm SRAM (PSM) Source:
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15. Statistical Dopant Placement
[Bernstein et al, IBM JRD 2006]
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16. Random Trans-to-Trans
Random dopant fluctuation
Local oxide variation
Line edge roughness
Etch and growth rates
Stochastic process
Transistors differ from each other in random ways
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17. Source: Noel Menezes, Intel ISPD2007
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18. Impact Changes parameters Change transistor behavior W, L, tOX, Vth W?
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19. Example: Vth Many physical effects impact Vth
Doping, dimensions, roughness
Behavior highly dependent on Vth
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20. Vth Variability @ 65nm [Bernstein et al, IBM JRD 2006]
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21. Impact of Vth Variation?
Higher VTH?
Not drive as strongly
Id,sat (Vgs-VTH)2
Performance?
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22. Impact Performance Vth  Ids  Delay (Ron * Cload)
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23. Impact of Vth Variation
Think NMOS Vgs = Vdd
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24. FPGA Logic Variation Altera Cyclone-II Xilinx Virtex 5 65nm 90nm
[Tuan et al. / ISQED 2010]
[Wong, FPT2007]
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25. Impact of Vth Variation?
Lower VTH?
Not turn off as well  leaks more
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26. 2004
Borkar (Intel) Micro 37 (2004)
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27. Operation
Temperature
Voltage
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28. Temperature Changes Different ambient environments
January in Maine
July in Philly
Air conditioned machine room
Self heat from activity of chip
Quality of heat sink (attachment thereof)
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29. Self Heating Borkar (Intel) Micro 37 (2004)
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30. Thermal Profile for Processor
[Reda/IEEE Tr Emerging CAS v1n2 2011]
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31. Temperature (on current?)
High temperature
More free thermal energy
Easier to conduct
Lowers Vth
Increase rate of collision
Lower saturation velocity
Lower saturation voltage
Lower peak Ids  slows down
One reason don’t want chips to run hot
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32. Temperature and Ids
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33. Temperature (leakage?)
High temperature Lowers Vth
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34. Voltage Power supply isn’t perfect Differs from design to design
Board to board?
How precise is regulator?
IR-drop in distribution
Bounce with current spikes
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35. Aging
Hot Carrier
NBTI
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36. Hot Carriers Trap electrons in oxide Also shifts Vth
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37. NBTI Negative Bias Temperature Instability
Interface traps, Holes
Long-term negative gate-source voltage
Affects PFET most
Increase Vth
Partially recoverable?
Temperature dependent
Another reason not to run hot.
[Stott, FPGA2010]
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38. Measured Accelerated Aging (Cyclone III, 65nm FPGA)
[Stott, FPGA2010]
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39. Coping with Variation
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40. Variation See a range of parameters L: Lmin – Lmax
Vth: Vth,min – Vth,max
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41. Impact of Vth Variation
Higher VTH
Not drive as strongly
Id,sat (Vgs-VTH)2
Lower VTH
Not turn off as well  leaks more
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42. Variation Ion,min=Ion(Vth,max) Margin for expected variation
Must assume Vth can be any value in range
Speed  assume Vth slowest value
Ion,min=Ion(Vth,max)
Id,sat (Vgs-Vth)2
Probability Distribution
VTH
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43. Gaussian Distribution
From:
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44. Impact Given What maximum Vth should expect to see for a circuit of
Vth,nom = 250mV
Sigma 25mV
What maximum Vth should expect to see for a circuit of
100 transistors?
1000 transistors?
109 transistors?
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45. Class ended here
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46. Variation See a range of parameters Validate design at extremes
L: Lmin – Lmax
Vth: Vth,min – Vth,max
Validate design at extremes
Work for both Vth,min and Vth,max ?
Design for worst-case scenario
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47. Margining Also margin for Temperature Voltage Aging: end-of-life
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48. Process Corners Many effects independent Many parameters
With N parameters,
Look only at extreme ends (low, high)
How many cases?
Try to identify the {worst,best} set of parameters
Slow corner of design space, fast corner
Use corners to bracket behavior
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49. Simple Corner Example What happens at various corners? 350mV Vthp
Vthn
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50. Process Corners Many effects independent Many parameters
Try to identify the {worst,best} set of parameters
E.g. Lump together things that make slow
Vthn, Vthp, temperature, Voltage
Try to reduce number of unique corners
Slow corner of design space
Use corners to bracket behavior
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51. Range of Behavior Still get range of performances
Any way to exploit the fact some are faster?
Probability Distribution
Delay
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52. Speed Binning Sell Sell cheap nominal Discard Sell Premium
Probability Distribution
Delay
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53. Midterm 1 Contents should not be a surprise Identify CMOS/non-CMOS
Identify CMOS function
Any logic function  CMOS gate
Noise Margins
Transistor Equations
All regions and identify operating regions
variation
Circuit quasistatic configuration and switching delay
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54. Admin HW4 First midterm next Monday Previous midterm Review on Sunday
Solutions linked to 2011 syllabus
Solutions linked to 2010 syllabus
But only one midterm in 2010 so parts more advanced than where we are now
Review on Sunday
Time?
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55. Idea Parameters Approximate Differ Robust design accommodates
Chip-to-chip, transistor-to-transistor, over time
Robust design accommodates
Tolerance and Margins
Doesn’t depend on precise behavior
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