1. 3.3.3 Computer architectures
OCR A Level F453: Computer architectures
3.3.3 Computer architectures
a. describe classic Von Neumann architecture, identifying the need for, and the uses of, special registers in the functioning of a processor;
b. describe, in simple terms, the fetch/decode/execute cycle, and the effects of the stages of the cycle on specific registers;
c. discuss co-processor, parallel processor and array processor systems, their uses, advantages and disadvantages;
d. describe and distinguish between Reduced Instruction Set Computer (RISC) and Complex Instruction Set Computer (CISC) architectures.

2. 3.3.3 Computer architectures
OCR A Level F453: Computer architectures
3.3.3 Computer architectures
Computer architecture just describes the different components of a computer and how they connect together.
You need have covered some of this information already in F Hardware.

3. OCR A Level F453: 3.3.3 Computer architectures
a. describe classic Von Neumann architecture, identifying the need for, and the uses of, special registers in the functioning of a processor;
b. describe, in simple terms, the fetch/decode/execute cycle, and the effects of the stages of the cycle on specific registers;

4. Von Neumann architecture
OCR A Level F453: Computer architectures
Von Neumann architecture
John Von Neumann was a mathematician and one of the first Computer Scientists.
He designed a computer that could store data, and programs in the same format in the same piece of memory. Most modern computers still operate on this principle.
His computer included a single Control Unit to manage the process, specialist registers and a method of input & output along side this central memory.
The central idea behind his design was the data or instructions stored in memory could be fetched, decoded and executed by the processor until a task was completed.

5. Fetch, Decode, Execute cycle
OCR A Level F453: Computer architectures
Fetch, Decode, Execute cycle
John Von Neumanns design for the operation of a computer processor involved three stages.
Fetch - Instructions or data are fetched from memory. They travel between main memory and the ALU using buses.
Decode - Once the instructions or data have been fetched they are translated ready for execution.
Execute - Finally the instructions are carried out by the processor.

6. OCR A Level F453: 3.3.3 Computer architectures
Specialist registers
As well as main memory and a control unit the Von Neumann architecture also made use of a number of specialist registers
& buses, including:
Memory Address Register(MAR)
Memory Data Register (MDR)
Current Instruction Register (CIR)
Accumulator
Interrupt Register
Control Bus
Address Bus
Memory Bus
This information was covered in F Hardware.

7. OCR A Level F453: 3.3.3 Computer architectures
c. discuss co-processor, parallel processor and array processor systems, their uses, advantages and disadvantages;

8. OCR A Level F453: 3.3.3 Computer architectures
Co-processor
A co-processor is an additional processor in the computer used for a specific task.
They increases the speed of the computer as the co-processor can process one task whilst the main processor is executing another.
Any good gaming PC will have a graphics processor to take deal with graphics processing whilst the main PC executes the rest of the game.

9. OCR A Level F453: 3.3.3 Computer architectures
Parallel processors
In parallel processing two or more processors work together to perform a single job. The job is split into smaller tasks which are executed simultaneously by both processors (any task can be processed by any processor).

10. OCR A Level F453: 3.3.3 Computer architectures
Array processors
Array processors are designed to execute the same instruction on several pieces of data simultaneously.
This means that operations are carried out very quickly.
They are often used in weather forecasting as the same instruction can be carried out on many pieces of data simultaneously.

11. OCR A Level F453: 3.3.3 Computer architectures
d. describe and distinguish between Reduced Instruction Set Computer (RISC) and Complex Instruction Set Computer (CISC) architectures.

12. Reduced Instruction Set Computer (RISC)
OCR A Level F453: Computer architectures
Reduced Instruction Set Computer (RISC)
RISC processors only have a small range of instructions available to them. Most of these are designed to carry out one simple, specific task (usually in a single clock cycle).
The Raspberry Pi is a good example of a RISC architecture.

13. Complex Instruction Set Computer (CISC)
OCR A Level F453: Computer architectures
Complex Instruction Set Computer (CISC)
CISC processors only have a huge range of instructions available to them. Many of these instructions actually carry out several lower level operations in a single command.
Because of their complexity some of these instructions can take many clock cycles to execute.

14. CISC Vs RISC CISC architectures tend to be more expensive than RISC.
OCR A Level F453: Computer architectures
CISC Vs RISC
CISC architectures tend to be more expensive than RISC.
Because of their complex instruction set some programs will run slower on CISC.
But a single CISC instruction might carry out the equivalent of several RISC instructions.