1. Meeting at CERN
March 2011

2. Goals of AMchip04 Increase number of buses, 8 input buses with 15bits
Change output bus from 18 bits to 15bits
Add pattern disable feature
For yield management
Add 3 Don’t Care bits / layer
Optimized for density, speed, cost
Density expected: ~8K patterns/12mm^2
speed: > 80MHz MHz
Core power: expected 1W /100K
IO power (?):

3. Global simulations (top down)
Global level simulation (change freq)… available to every group
C++ level functional simulation
Schematics/verilog functional level simulation
with timing info at cell level, but zero delay for
nets
Netlist level simulation with layout info, with delay info of nets  more realistic
Includes full-custom models (critical)

4. Simulations (bottom up)
3 full-custom blocks in the core logic
CAM layer
Majority logic
Readout logic (fisher tree, address and bitmap encoder)
End of March: Simulation of each piece by itself (done for CAM layer)
Manual simulations to verify functionality, timing, power consumption
End of March: first boundary scan code
End of March: CAM block simulation (in progress)
64 pairs of layers, + dummy layer, current bias
Simulation time several hours
End of March: Integrate these pieces together
End of April: Integrated simulation with limited area
4 patterns + dummy layers
Majority
Readout logic
End of April: Integration with global standard cell logic
End of May: Prepare digital model(s) of full custom pieces or full custom block
End of May: Verification of models (critical for success)
Will require a workshop to gather designers in the same place
Combine global logic with digital models  global simulation
Timing reports

5. Schedule/milestones (from feb 23rd)
end of  March:
a first version of the boundary scan is available
preliminary layout of the majority logic cell available
first version of the CAM-block available
starting beginning of April work on a first integration of the chip
end of April: after simulation and debugging…
a final version of the boundary scan is available 
a complete layout of the majority logic cell
final design for the CAM-block available
starting beginning of May work on the final integration of the chip
end of May: successful integration of all pieces
during May test and simulation of the integrated design. 
during June based on simulation decide what adjustments are needed
end of June: completed all simulations of the chip
the final and integrated chip should be completely simulated and approved.
early July submission