1. Baby-Mind SiPM Front End Electronics
UPDATED STATUS
Yannick FAVRE University of Geneva
Etam Noah
A. Blondel

2. Outline Unige library overview Hardware status FPGA firmware status
USB3 host software status
Measurements
Global status & conclusion

3. Unige library overview
USB3 communication
Unige USB library components:
On board:
Cypress FX3 USB3 microcontroller
Unige firmware for FX3
Unige VHDL library
On host
Cypress USB driver
Unige C# library
Unige Protocol handling over USB3 Endpoints
Protocol class within Unige C# library
Encoder/decoder entities within Unige VHDL library
Hardware + software Overview
Typical usage of library
in FPGA design

4. Hardware status : ready for 1st physics measurement
STATUS : 2 board tested, 3 board to be started
LV Power supplies : OK
FPGA programming : OK
USB µC & interface : OK
ASIC : OK
Slow control : OK
HV DAC : OK
Fast Internal Triggers & OR32 : OK
Fast Internal Triggers OUT: TB Tested
Preamp, Shaper, Hold, Mux OUT LG/HG : OK
ADC : OK
ADC signal conditioning : Modified with 1 glued piggy board / ASIC
ASIC baseline subtraction, ADC protection, gain change for best ADC resolution % ASIC output
HV : OK
Gigabit : TBT
SiPM finger plots : OK

5. FPGA firmware status
ALTERA ARIA5 (BGA896) A7 on proto, A3 or A5 on production
- Code : Quartus dev. tool, VHDL behavorial (design reuse) + some FPGA IP specific modules

6. FPGA firmware status Fully simulated with Modelsim
Tested on Hardware + USB communication
Partially Tested on Hardware + USB

7. USB3 host software status
C# (ms visual studio)
Versatile architecture designed for reuse:
Low level classes for protocol communication handling
Hardware slow control direct building & mapping through abstraction classes
Direct connection to FPGA/ASIC trough USB3
Simple building & hardware mapping
File handling (HML open/save File)
GUI direct connection with slow control variables declared from abstraction classes :
Simple building
Automatic coherency check (Min, Max)
Ex : boolean connected to a checkBox, Byte connected to a textBox …
Readout Save to file:
2.5Gb/s to 3Gb/s achieved from USB3
C# Scripting/Batching
Command line
Labview virtual instrument
Linux

8. USB3 host software status
Readout & general tab
1 Software engineer at 20% (1 day/week)
Basic functionalities : OK
Slow control
Readout to File
Scripting : End of March
Library Class : End of June
Cleaning and harmonization
Generic application form from library
Linux portability: End of Summer
Unified graphical objects migration
USB driver abstraction class
Command line access: End of Summer
Labview virtual instrument : TBD
ASIC0 slow control tab
Scripting

9. Measurements & optimization
FPGA:
96-CH LG+HG Mux ~10us (1/4MHz x 32-ch + 2µs latency)
DAQ mode Compare:
Triggered by 3xOR32 from ASICs
Use HOLD signal to latch analog signal on shaper peak
Each channel can be compared to baseline computed + user threshold and sent to readout
DAQ mode Compute:
Free running when not in compare mode
No hold signal
Used for independent CH baseline computation (Low Pass filter)
FPGA & HW Optimization
ADC sampling point optimization (1/4)
Noise on ASIC 3.3VA :
poor ASIC Common Mode Rejection Ratio
=> LDO capacitor displacement
=> Self shielding (no so improving)
=> for next board version
CH0
CH1 …
ASIC HG/LG MUX

10. Measurements SiPM: Compare mode only: DAQ: HV=67.65V (135)
1 CH connected at a time
Compare mode only:
Static mode (no baseline subtraction)
HG path only, HG=55
Fast Shaper on HG, OR32 output, Peak detector mode, THD DAC10b=200
ASIC Shaper Time Constant = 12.5s (1)
FPGA hold = 15ns (6)
DAQ:
256K samples, t<10s / channel
ASIC0
(CH1/5/25)
ASIC1
(CH1/5/25)
ASIC2
(CH1/5/25)

11. Status conclusion Board hardware : 2 board tested
3 boards to be started & tested : mid March
Independent ASIC trigger tests : begin. April
FPGA size validation, power consumption, Gigabit links : TBD
FPGA firmware : Analog Readout + Slow Control on USB OK
2rd version : + Timing : begin. April
3rd version : + USB multi-board chain : begin. May
4th version : + baseline computation within FPGA : TBD
5th version : + Gigabit multi-board chain : TBD
USB3 software : Analog Readout + Slow Control on USB OK
Scripting: end March
Class Cleaning, harmonization : end June
Linux : end September
Next Board hardware : Design start after beam test in July (need feedback)
ASIC analog signals conditioning & ASIC input protection
Analog input connectors stage
Trigger chain
FPGA remote FW update
Ethernet/Optic link ?

12. BACKUP SLIDES

13. FRONT-END BOARD 96 coax. connectors (84 used) 3 CITIROC ASICs 32-ch
12-bits 8-ch 40Ms/s/ch ADC
Altera ARIA5 FPGA :
Timing : 2.5ns resolution
Analog : 8µs for 96-ch LGain & HGain
HV, ASIC T° + board T° + RH%
Readout/Slow control on USB3 and/or Gigabit RJ45 chain
External propagated Trig/sync. Signal
Power supplies (HV/LV)
240
24V
LVs
USB
RJ45
FPGA
ADC HV
130
ASICs
96 coax. (top/bot)
FEB prototype

14. READOUT & SLOW CONTROL – CABLING OPTIONS
- Number of chained FEB depends on events frequency and bandwidth limit => application specific
- Ex : 8 chained FEB for Baby-Mind (VRB limitation)

15. CITIROC BLOC DIAGRAM

16. FPGA Architecture

17. Protocol
Readout
Slow Control