1. Timing issues

2. Why we should check timing ?
RTL Transfer
add <= a + b;
Should meet
the device
specifications
Logic level
Physical device

3. What is setup ? What is hold ?
Logic
The “window” on which
the input data
should be stable !!!
clock
clock
clock

4. Timing Conditions: Set-up
Give enough time to sample the data then close pass gate D
CLK Q# q
weak inverter

5. Timing Conditions: Hold Time
Give enough time to close pass gate then change data D
CLK Q# q
weak inverter

6. Timing conditions: Summary
Hold
CLK
DATA

7. Setup checks Setup: 1ns 1 2 4 1 3 10ns 1 clock clock clock 4ns 2ns 1ns

8. Setup checks (cont.) from the 1st edge of the clock Output delay
T setup
Output delay
Logic
+ Propagation delay
+ Setup time
clock
< Cycle time
T cycle
Setup relationship is
from the 1st edge of the clock
in the “launch” flip-flop to the
subsequent capture edge of the clock
within the “receive” flip-flop
clock
clock

9. Setup checks : critical path
Setup: 1ns
4ns
8ns
1ns
12ns
clock
The critical path
for setup checks
is the longest path
10ns
clock 1 4 8 12
clock 1

10. Hold checks
Hold: 1ns
0.3ns
clock
clock .3
10ns 1
clock

11. Hold checks (cont.) between the release edge of Output delay
T hold
Output delay
+ Propagation delay
- Hold time
clock
> 0
Cycle time
Hold relationship is
between the release edge of
the “launch” clock
to the “receive” clock
preceding the setup check
clock
clock

12. Hold checks : Critical path
Hold: 1ns
4ns
0.7ns
0.3ns
clock
The critical path
for hold checks
is the shortest path
10ns
clock .3 .7 4 1
clock

13. Setup -> Max delay Hold -> Min delay
T setup
Max Output delay
Setup
Max
Logic
+ Max Propagation delay
+ Setup time
clock
< Cycle time
T hold
Min Output delay
Hold
Min
+ Min Propagation delay
- Hold time
clock
> 0

14. Timing exceptions Multi-cycle path Control Logic Clk#1 Clk#1 Clk#1

15. Timing exceptions (cont.)
Control
Logic
False path
Clk#1
Clk#2
Clk#1
Clk#2

16. Modeling a non-ideal clock#2
Clk#1 #1 ??
Clk#1
Clk#2
Clk#2
clock

17. Setup checks with a non-ideal clock
T setup
Output delay
Logic
+ Propagation delay
+ Setup time
clock
< Cycle time
- Clock delay
T cycle
clock
clock

18. Hold checks with a non-ideal clock
T hold
Output delay
+ Propagation delay
- Hold time
clock
> 0
+ Clock delay
Cycle time
clock
clock