1. Supplement on Verilog Sequential circuit examples: FSM
Based on
Fundamentals of Digital Logic with Verilog Design
and Fundamental of Logic Design
Chung-Ho Chen

2. A Simple Circuit Using Blocking Assignment
module simple (x1, x2, x3, Clock, f, g);
input x1, x2, x3, Clock;
output reg f, g;
Clock)
begin
f = x1 & x2;
g = f | x3;
end
endmodule
A rising edge, latch f = x1&X2, and
latch g = (x1&x2) | x3.

3. Non-Blocking Assignment
module simple (x1, x2, x3, Clock, f, g);
input x1, x2, x3, Clock;
output reg f, g;
Clock)
begin
f <= x1 & x2;
g <= f | x3;
end
endmodule
taking previous f
// reversing f and g
statement makes no
difference in result.
// Non-blocking assignment, f and g are updated at the same time.
Meaning that, g must take a previous f.

4. Moore Machine FSM y: present state Y: next state
When y = 11, Y is don’t care
// enter A after reset
// at State C, z = 1

5. Moore Machine FSM y: present state Y: next state
//Combinational using blocking assignment

6. Moore Machine FSM y: present state
// non-blocking assignment for sequential ckt.

7. Mealy Machine FSM
Output z depends on input (w) and
state y.

8. Arbiter FSM Arbiter: who arbitrates the requests and issues grants.
requests from bus masters
Arbiter FSM
grant signals to requesters
y present S, Y next S
Arbiter: who arbitrates the requests and issues grants.
In this example, r1: highest priority, then r2, then r3.
r1>r2>r3

9. Mealy-Type Serial Adder: Use State to Keep Carryout
Use shift register to keep operand X and Y x y

10. Serial Adder Block Diagram
Shift register with enable control
Load initial value
Shift w into the left most bit

11. Shift Registers for X, Y, and Sum
module serial_adder (X, Y, Reset, Clock, Sum);
input [7:0] X, Y;
input Reset, Clock;
output wire [7:0] Sum;
reg [3:0] Count;
reg s, PS, NS;
wire [7:0] QX, QY; // for connection to FSM
wire Run;
parameter S0 = 1’b0, S1 = 1’b1;
shiftrne shift_X (X, Reset, 1’b1, 1’b0, Clock, QX);
shiftrne shift_Y (Y, Reset, 1’b1, 1’b0, Clock, QY);
shiftrne shift_Sum (8’b0, Reset, Run, s, Clock, Sum);
Shift 0 into the lsb
Shift s into the SUM reg

12. The Rest s = x xor y xor cin |x //equivalent to 1 | 0 | 1 | 0
// Adder FSM
// Output and next state combinational circuit
QY, PS)
case (PS)
S0: begin
s = QX[0] ^ QY[0]; // current state C is zero
if (QX[0] & QY[0]) NS = S1;
else NS = S0;
end
S1: begin
s = QX[0] ~^ QY[0]; //
if (~QX[0] & ~QY[0]) NS = S0;
else NS = S1;
default: NS = S0;
endcase
// Sequential block
Clock)
if (Reset) PS <= S0;
else PS <= NS;
// Control the shifting process
if (Reset) Count = 8;
else if (Run) Count = Count - 1;
assign Run = |Count;
endmodule
s = x xor y xor cin
|x //equivalent to 1 | 0 | 1 | 0
if x=4’b 1010

13. Moore Type Serial Adder
S00 and S01 for ci-1 = 0
S10 and S11 for ci-1 = 1
xiyi