1. Choices in Designing an ISA
Uniformity. Should each instruction
Be the same length (in bits or bytes?)
Take the same time to execute?
Complexity.
How many different instructions?
How closely linked to High Level languages?
Tradeoffs – Complex Instructions
Take up less code memory to store them
Need a rather complex CPU design
CBP 2009
Comp 3014 The Nature of Computing

2. Instruction Encoding Example
destination
All Sam’s instructions take up 32 bits.
opcode
Source regs
add rd rs rt
unused
Sam’s instructions start with the opcode then the destination reg- ister then the source register
rd <- rs + rt
e.g. add r3, r1, r2 means r3 = r1 + r2
First 6 bits for the opcode.
010110
00011
00010
00001
unused 3 2 1
CBP 2009
Comp 3014 The Nature of Computing

3. Intel 80x86 ISA The most popular of all
1971: Intel invents microprocessor 4004/8008, 8080, 8085
1975: Major design effort for new 16-bit ISA, (iAPX432) but …
1978: 8086 dedicated registers, segmented address, 16-bit
8088; 8-bit version of 8086 added as after thought
1980: IBM selects 8088 as basis for IBM PC
1980: Intel 432 finally ready but…
1980: 8087 floating point coprocessor:
1982: bit address, protection, memory mapping
1985: bit address, 32-bit GP registers, paging
1989: 80486
1992 Pentium
1995 Pentium Pro
1997 Pentium Pro with MMX multimedia acceleration
CBP 2009
Comp 3014 The Nature of Computing

4. Some x86 instructions These look rather like Sam’s RISC ops
mov ax , [bx + c]
mov [ax] , bx
add ax , bx
add [bx] , ax
These look rather like Sam’s RISC ops
Let’s compare the RR and RM ISA’s. Clearly RR needs more memory while the RM uses stronger operations
But this is not. Here the contents of ax is being added straight into memory ! The x86 is a register – memory ISA and Sam is a register – register ISA
ldi r1 , a
ldi r2 , b
add r3,r1,r2 st r3 , b
mov ax, a
add b,ax
Sam
Intel x86
CBP 2009
Comp 3014 The Nature of Computing

5. Variable Length Instructions0%
10%
20%
30% 1 2 3 4 5 6 7 8 9 10
All Sam’s instructions had the same length, 32 bits. This is also true for other RISC ISA’s such as SPARC and MIPS. Compare this with the x86 instruction vary from 1 to 17 bytes. Here’s some stats.
Clearly long complex instructions are used infrequently
Instruction Length (bytes)
But the use does depend on the app.
Expresso
Gcc
Spice
Nasa
Frequency of use
CBP 2009
Comp 3014 The Nature of Computing

6. Variable Time Instructions
Here’s a timing diagram for an Intel add
add ax , [bx + c] T1 T2 T3 T4 T5
Fetch
Decode, Reg Op
ALU
Mem Access
Reg Write
[bx + c]
ax = ax + mem[..]
… and the second to actually add memory to register ax
We need two adds. The first to get the address summed up …
CBP 2009
Comp 3014 The Nature of Computing

7. Potent x86 Instructions 1.Application 2.High-Level Language (‘C’)
Greenspan
strcmp(str, Greenspan);
2.High-Level Language (‘C’)
mov x,2
Immediate to memory 6
xlat x
Translate al via table 1
imul x
Multiply memory with ax 4
inc x
Increment memory by 1
Repne scasb
Scan string for match !
various
3.Intel ISA code
CBP 2009
Comp 3014 The Nature of Computing

8. Top 10 Intel x86 Instructions
Rank Instruction Usage
1 load 22% 2 conditional branch 20% 3 arithmetic / logic 19% 4 compare 16% 5 store 12 % 6 move reg - reg 4% 7 call - return 2%
We see that most instructions are Simple load, store, calculate, branch. None of Intel’s potent stuff figures here. So why did Intel design instructions no-one uses ?
CBP 2009
Comp 3014 The Nature of Computing

9. Semantic Gap Twixt HLL and ML
In the 1970’s Hardware costs decreased.
So we got faster CPUs but Memory was expensive.
ld r1,B ld r2, ld r3,[r1 + r2] add r4,r4,r3 addi r2,r2,1 str r4,[r2+5] … …
add r4,r3,r2
Bigger programs means more expensive programs
Shortage of Good Programmers
Unreliable Software
Response : Reduce programming Costs
Develop powerful HLL easy to learn so no mistakes
But is Semantic Gap between HLL and ML
Software runs inefficiently - Poor Performance
Compilers become Complex
So Close the Semantic Gap
Machine executes HLL constructs in hardware
Lots of addressing Modes
Add the column of sales figures
But this potent stuff is not being used !
CBP 2009
Comp 3014 The Nature of Computing

10. 1980 Berkeley Patterson RISC (SPARC) 1981 Stanford Hennessy MIPS
ISA R&D into the 80’s
Let’s downshift and make things simpler …
Use simple instructions, load, store, add
Many of these will do one x86 potent op
Need more memory, but memory is becoming cheap
More CPU cycles, but can still be faster
1980 Berkeley Patterson RISC (SPARC)
1981 Stanford Hennessy MIPS
- Easy to Decode Ops Fast Issue Rate Only load and Store references memory Lots of registers
Emerging Design Guidelines
CBP 2009
Comp 3014 The Nature of Computing