1. Discussion after electronics parallel session
Dominique Breton
SuperB workshop – SLAC – February 2008
Dominique Breton – SuperB workshop – SLAC – February 2008

2. Agenda of the electronics parallel session
Trigger/DAQ: Stephen Luitz
SVT: Giuliana Rizzo
DCH: Matt Weaver
PID: Dominique Breton on behalf of Jerry Va’vra
EMC: Dominique Breton
IFR: Angelo Cotta Ramusino
Radiation topics: Dominique Breton
All: discussion and preparation of the summary for the plenary
Dominique Breton – SuperB workshop – SLAC – February 2008

3. About radiation hardness (1)
In the CDR: « Because of the very high event rates anticipated, it will be important to push as much of the task of feature extraction as possible into intelligence in the front-end electronics ».
Particles (especially neutrons) above a few MeV may interact with silicon.
Neutron flux (produced by particles hitting something massive) should be directly linked to luminosity.
The upgrade of BaBar drift chamber electronics showed that putting intelligence inside this detector pushes to take the radiation problems into account.
Single Events and total dose are the two subjects of concern.
It looks like, besides SVT, total dose should not be a main worry, except maybe for in-detector electronics making use of regulators.
Single Events can be split into two families:
Single Event Upsets: non destructive. May happen in the memory cells, and thus mainly concern data and the configuration of FPGAs.
Single Event Latchup: potentially destructive. Needs higher energy.
If simulations (to be performed) show that the SEU rates may be high, our electronics has to be mitigated for it.
If SEL may occur, all used circuits have to be validated for this kind of environment (already validated COTS, beam test self-validation, …)
Dominique Breton – SuperB workshop – SLAC – February 2008

4. About radiation hardness (2)
Sensitivity to Single Events rapidly
increases when silicon technology
gets smaller.
Mitigation methods depend on the expected rate of SEUs:
If the rate is low, standard FPGA can be used
Mitigation must concern both user data and configuration:
Concerning configuration, the latter has to be checked regularly and reloaded if a bit flip was detected (=> source of deadtime !)
Concerning user data, TMR (triple modular redundancy) methods can be used in the FPGA code, as well as encoded redundancy in the RAMs.
If the rate is higher, radiation tolerant families have to be used (like ACTEL’s EEPROM based ProAsic FPGAs).
We need simulations to get a map of the radiation levels in order to make a safe decision on these points at an early stage of the design => to be put on the to do list.
Dominique Breton – SuperB workshop – SLAC – February 2008

5. About Trigger and DAQ (1)
The main worry for DAQ experts is the mean size of the event.
If the event size goes far above 75kBytes, the proposed architecture may not match the trigger rate requirements.
It is important to convince ourselves that the simulated background rates are valid (there seems for instance to be some worry about Touschek-linked background not only for SVT but also for DCH and EMC)
The other source of uncertainty is the number of channels of the new subdetectors.
For instance, the number of channels of the TOF may reach if the MCPPMT pixels are not ganged together, which may otherwise decrease their resolution.
> this forces to perform a very effective filtering of data before sending them to DAQ
Trigger rate and trigger acceptance window correlate directly with data rate (is the 1µs value mandatory ? )
L1 central Trigger hardware is a subsystem by itself.
Dominique Breton – SuperB workshop – SLAC – February 2008

6. About Trigger and DAQ (2)
We tried to define the potential boundary between front-end and DAQ.
The natural location seems to be the optical fiber, even if some feature extraction has to be performed on the detector side.
The detector side of the readout system however will have to cope with common rules defined for the whole experiment.
The hardware located on that side should however become common if feasible or necessary.
For instance, if we want to be able to program the FPGAs on the detector through the control fiber:
a dedicated common solution could be studied therefore.
If it has to sit in an irradiated environment, this solution would have to be rad-tolerant.
Dominique Breton – SuperB workshop – SLAC – February 2008

7. Dominique Breton – SuperB workshop – SLAC – February 2008
About SVT
The background-linked occupancy is a main worry, especially in layer0.
For efficiency and power reasons, the SVT very front-end readout is based on a data-driven architecture.
However, the goal is to have a fully triggered architecture for data readout.
SVT track precursors would be of a great help for level 3 trigger
=> Intermediate electronics boards could be inserted as in BaBar on the data path close to the detector in a much less irradiated environment, taking care of:
Feature extraction if necessary
Preparing the track precursors thanks to associative memories
Links between the SVT and these boards could be fast differential copper pairs.
L1 buffers could be located either there or in-detector
Dominique Breton – SuperB workshop – SLAC – February 2008

8. Dominique Breton – SuperB workshop – SLAC – February 2008
Requirements on link speed reduced by 1/10 Assuming 1 us window and 100 KHz LV1 rate
Layer
flux
(Hz/cm2)
1 us
Occupancy
HDI Link speed
Read all data
Data driven
( bit/s/ROS)
Read only LV1 evt
hit/evt
bit/evt
(with 25 bit word)
0- Striplets
5.00E+06
4.50E-02
8.64E+08
8.64E+07
1.11E+03
2.76E+04
0- MAPS
1.25E-04
8.19E+08
8.19E+07
1.25E+03
2.62E+04 1
2.00E+05
2.00E-02
4.48E+08
4.48E+07
4.30E+02
1.08E+04 2 3
1.00E+05
6.40E+08
6.40E+07
6.14E+02
1.54E+04 4
noise occu
1.00E-02
1.60E+08
1.60E+07
3.69E+02
9.22E+03 5
4.15E+02
1.04E+04
evt size L1-5
7kByte
evt size L0
3.3kByte
Simulated Background track rate
Present BaBar data
Similar in SuperB L1-L5
BaBar SVT evt size
L1-L5 ~ 9 kByte
Dominique Breton – SuperB workshop – SLAC – February 2008

9. Examples of different possible implementations for SVT readout
Pixel sensor +
front-end chips
On Detector
Off Detector
HDI
Power/Control
DAQ
Data-driven only: untriggered
Fast link
Data
L1 buffers
Triggered inside SVT
HDI
Power/Control
DAQ
Triggered inside SVT
+ L3 track precursors
link
Data
Inside Detector
Close to Detector
Off Detector
HDI
Power/Control
Ass
Mem
DAQ
Copper links
link
Data ?
Dominique Breton – SuperB workshop – SLAC – February 2008

10. Dominique Breton – SuperB workshop – SLAC – February 2008
About EMC barrel
Overall triggered readout is required.
The weak point on current BaBar EMC barrel seems to be the I/O board because of its mechanical design.
ADC board connectors provide at the same time the electrical and mechanical connections
Cooling is tricky and interferes with mechanical stability
Power budget is also a problem there.
=> a possible solution towards a triggered architecture and reduced power in detector has been evoked
=> current I/O boards could be removed and pushed farther on the data path close to the detector, where they would take care of:
L1 buffering
Feature extraction
Trigger pre-processing
Dominique Breton – SuperB workshop – SLAC – February 2008

11. Ideas for EMC barrel New I/O board
On-Detector
New I/O board
On-Crystal
In-Detector
Off-Detector
DF + L1 buffer
Copper link
ADC Board
IO Board
16 fibers
Preamp
DAQ
4 ea
Barrel: 5,760 ea
Barrel: 480 ea
Barrel: 80 ea
30 links
Trigger PP
16 fibers
To Trigger
8 ea
The most critical part from the mechanical point of view
Barrel: 16 ea
New I/O board
Located outside the calorimeter but close to it => less accessible for particles => lower potential radiation level.
Concentrates data flowing continuously from 30 ADC boards through serial copper links
Receives the L1 trigger
Performs digital filtering
Houses the L1 latency buffers
Houses trigger pre-processor elements
Sends data to DAQ and trigger elements via two different optical links
Concerning the EC, the same kind of design could be envisaged, maybe with a different implementation.
Dominique Breton – SuperB workshop – SLAC – February 2008

12. Dominique Breton – SuperB workshop – SLAC – February 2008
About FCTS
If we want to keep the clock distribution « à la BaBar », we may get into trouble when we aim at getting a time precision of about 10ps for the new subdetectors.
Mixing clock and data on the same link indeed induces jitter on the clock recovery.
=> we have to check that the deserializers we feel like using comply with this requirement
=> otherwise, clock recovery PLLs have to be used for the concerned subdetectors
If electronics sits in an irradiated environment, this is not an easy job, as PLLs don’t really like SEUs …
If we have time LSB of the order of 10ps, what’s the reasonnable size of the time counters ?
This has a consequence on the data size.
Couldn’t the machine RF frequency be a simple and good candidate for the T0 of the TOF measurement ?
The remaining uncertainty is only linked to the ultimate size of the beam bunches at the IP.
Dominique Breton – SuperB workshop – SLAC – February 2008

13. Dominique Breton – SuperB workshop – SLAC – February 2008
Conclusion
What is our roadmap for homework towards Elba, besides subdetector R&D ?
Circulating a draft for trigger/DAQ requirements ?
Learning more about radiation levels ?
Getting farther into subsystem electronics architecture with respect to common requirements?
Is there any new urgent R&D common subject emerging ?
What is our roadmap towards the TDR ?
Dominique Breton – SuperB workshop – SLAC – February 2008