1. The Control of Phase and Latency in the Xilinx Transceivers.
The Control of Phase and Latency in the Xilinx Transceivers
Paolo Novellini –

2. Agenda Xilinx Transceiver Overview Accurate Phase Control:
Block Diagram
Clocking Architecture
Non- disruptive Eyescan
Accurate Phase Control:
Phase Interpolator in TX and RX
XAPP1240: Non-integer Data recovery Unit based on Oversampling.
XAPP589: Using the serdes as a digital Cleanup PLL
Latency Control:
Control: Buffer Bypass Mode
Control and Equalization
Measurement

3. Transceiver Portfolio
Kintex
Kintex 7
Virtex
Virtex 7
Kintex
Kintex
UltraScale
Virtex UltraScale
Virtex
Kintex
UltraScale+
Kintex
Virtex
Virtex UltraScale+
GTY
GTY
30.5G
GTY
32.75G
16.3G
GTH
GTH
16.3G
GTH
13.1G
GTH
12.5G
GTX
28 nm
20 nm
16 nm
Continuous Operation Down to 500Mbit/s

4. Clocking Architecture
Quad Architecture for GTH and GTY
4 Channels per Quad
Channel PLL (CPLL)
1 per transceiver channel
2 to 6.25GHz
Half rate PLL for up to 12.5Gb/s
Common block
Two high performance LC PLLs
VCO frequency range:
QPLL0: 9.8 to 16.3GHz
QPLL1: 8.0 to 13.0GHz
Clock Selection
Each TX and each RX has an independent mux to select from the three clock sources
Dedicated recovered clock output, directly on the board.

5. In Silicon - System Analysis with Eye Scan Non-Destructive On-Chip Debug
Two Samplers in RX Path
Data Sampler at the eye center
Moveable Offset Sampler
Compare two samplers
2-D BER Eye built from error location
Eye Scan inside receiver on live data
Non-destructive
Post equalization – real margin at the data sampler!
BER Measurement
2-D Plot – offset both voltage and phase
Features
UltraScal Eye Scan
Horizontal Taps
64 at max rate, up to 512
Vertical Taps
256
Diagnostic Tool
IBERT, Custom logic

6. How Eye Scan Works Data Offset Bit Error? 1 Two Samplers in RX Path
Hard PCS Logic
SIPO
RX CDR
CLK +
Data
CDR +
Data
Sampler EQ
FPGA Fabric
#Samples
#Errors
Counter
Offset
Sampler
Voltage offset
Register
Access
XOR
Two Samplers in RX Path
Data Sampler :
same as regular CDR
Always in center of eye
Offset Sampler
Moveable sampler to trace the eye
If Data and Offset Sampler have different value, a Bit Error has occurred at the Offset Sampler!
# samples and #errors recorded in PCS counter
Allows non-destructive EyeScan on LIVE data w/o creating Data Errors
Data
Offset
Bit Error? 1

7. Example Backplanes: 40 Molex Impel Backplane
Vitals
No of Lanes: 8 (2 quads)
Line Rate – 25.78Gb/s
Material – Megtron 6
Length – 40in (inc line cards)
Loss – 30dB + 6dB

8. Phase Interpolator: Infinite Delay LineX
Sin (ωt)
Sin (ωt+φ) + X
90 deg shift C1 C2
Unbounded Phase Shift Possible!

9. TX and RX Phase Interpolator
Each Receiver has its own Phase Interpolator
Traditionally managed by the CDR logic
Can be manually controlled
Equivalent to ADC 1bit with fine phase control.
Each TX Serdes has its own Phase Interpolator
Can shift the TX phase back/forward in steps of 1UI/32
Infinite shift allowed
A continuous shift emulates a frequency change
This can work on top of the fractional PLL.
A TX serdes can be used as a fractional VCXO, with digital control.
Fine Unbounded Phase Shift = Frequency Shift.

10. Example 1: Fully Digital PLL based on TX PI (XAPP589)
The TX serdes can be seen as a digital VCO
With a Phase Detector implemented in fabric, we can slave the TX serdes (= VCO) to any reference clock
Bandwidth can be digitally controlled.
A fully digital Clean up, fully embedded in the FPGA.

11. Example 2: Non-Integer Data Recovery Unit (NIDRU) based on Oversampling – XAPP1240
REAL TIME PPM DIFFERENCE – resolution in fraction of Hz
LOCAL REFCLOCK PD LP
VCO
OVERSAMPLED DATA
PARALLEL DATA OUT
MGT RX (CDR DISABLED)
SERIAL DATAIN
SAMPLER
By using by RX Serdes as an ADC 1 bit, a digital CDR can be implemented in fabric
Rate, bandwidth and jitter peaking can be controlled dynamically.
Extends the serdes supported datarate down to 0 Mbit/s
BANDWIDTH
JITTER PEAKING

12. Latency Through a Serdes: The Problem
The latency through a serdes is not constant:
Depends on voltage and temperature.
Changes at each startup
What if an application requires a controlled latency?
Buffer Bypass mode, for RX and TX.
In General, a Serdes Changes Latency at Each Startup

13. RX Low Latency Mode: Fixed Rx Latency
Operated only at startup
RECEIVER
FABRIC
BIT SLIP
DATA DT DT
CDR
SIPO
FF VECTOR
DATA
(DOMAIN CROSSING)
FF VECTOR
CLK
CLK
CLK
Clock tree
DIV N
Delay Aligner
Operated only after reset

14. TX Low Latency Mode: Fixed Rx Latency
DATA DT
FF VECTOR
DATA
(DOMAIN CROSSING)
FF VECTOR
TX DATA
PISO
CLK
CLK
Operated only at startup PI
Clock tree
REFCLK
Delay Aligner
Operated only after reset
FABRIC
TRANSMITTER

15. TX Latency Equalization: The Problem
FPGA FABRIC
SERDES
TX 0 (application)
APPLICATION DATA (PARALLEL)
FIFO 0
TX PI 0
APPLICATION DATA (SERIAL)
Multiple transmitters have different latency, even if reset at the same time
How can I equalize their latency?
FLAG 0
REFCLK
FPGA FABRIC
SERDES
TX 1 (application)
APPLICATION DATA (PARALLEL)
FIFO 1
TX PI 1
APPLICATION DATA (SERIAL)
FLAG 1
REFCLK

16. TX Latency Equalization
FPGA FABRIC
SERDES
N BITS
FROM FABRIC
TO PISO
FIFO with M WORDS
WRITING ADDRESS
(WA)
READING ADDRESS
(WA) /M - /M
BUFG
FLAG
DIFFERENCE
(DOMAIN CROSSING HANDLED
WITH GRAY CODING)
TX PI
is this > threshold?
REFCLK
FIFO FILLING LEVEL
MONITOR CIRCUIT

17. TX Latency Measurement: Example
FPGA FABRIC
SERDES
FABRIC FIFO TX
BUFFER BYPASS MODE
TX SERIAL
W CLOCK
R CLOCK
FIXED LATENCY
PHASE DETECTOR
Moving the serdes FIFO to the fabric allows measuring its latency over time.
For RX section, we use a similar structure.

18. Conclusions
Many blocks are devoted to phase/latency control and measurement.
Do not hesitate to contact Xilinx in case you would like to discuss your own timing architecture.

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