1. Verification Details US Belle II WBS 1.03 Readout Electronics
Gary Varner
University of Hawaii

2. Waveform sampling ASIC
iTOP Readout
Waveform sampling ASIC
64 DAQ fiber
transceivers
8k channels
1k 8-ch. ASICs
64 “board stacks”
Low-jitter clock
512 channels/iTOP module (16)
8k channels/ TOP subdetector
4 Boardstacks/iTOP module
4 Carriers/Boardstack
4 ASICs (32 ch.)/Carrier
64 SRM

3. Key Performance Parameters (iTOP)
Tolerance
Threshold
Objective
Specification
Verification
70 Boardstacks
Good Channels
90%
98%
99%
Trigger threshold, efficiency, gain, noise
100%
Deadtimeless Occupancy 1%
2.5% 4%
Throughput during calibration
3.8%
Belle2link readout**
Single photon, fast feature extracted timing
100ps
50ps
35ps
Single photon laser scan
70.8 +/- 6.4 ps
Event Time Zero
30ps
Pulser timing across SuperKEKB Ref clock boundary
27.6 +/- 1.8 ps
Event Trigger timing
10ns
4ns
2ns
Trigger timestamping during single photon laser
8.2 +/- 1.0 ns
* 17 TOP Modules * 4 Boardstacks/Module = 68 Boardstacks (2 spares)
** >40MBytes/s sustained indefinitely (COPPER backend limit)
June 1, 2016
CD-4 Independent Project Review 3

4. iTOP Acceptance Criteria
IRSX ASIC
Noise test, pedestal test
All samples, windows operational
Timebase generator verification
DLL Feedback scan
Electrical (2-pulse timing) verification
SCROD and Carrier (electrical test)
IBERT and DRAM
Injected signal/amplifier chain gain
Integrated Boardstacks (laser test)
Single photon trigger efficiency and gain
Single photon timing
DLL Feedback scan
2-pulse timing (<25ps)
June 1, 2016
CD-4 Independent Project Review 4

5. iTOP Acceptance Testing
2x Carrier test stations at South Carolina, 1x backup in Hawaii
Laser test stand Hawaii
SCROD test stand in Pittsburgh
Firmware test at PNNL
Carrier test stand
Laser scan
June 1, 2016
CD-4 Independent Project Review 5

6. CD-4 Independent Project Review
Gain and Efficiency
June 1, 2016
CD-4 Independent Project Review 6

7. PerformancE summaries
June 1, 2016
CD-4 Independent Project Review 7

8. Example laser timing Residual
~31ps TDC+phase
SL-10 TTS ~35ps
IRSX electronics:
~33ps
Use SSTin period constraint to calibrate absolute timebase
June 1, 2016
CD-4 Independent Project Review 8

9. Threshold Scan (x4 gain trigger, using noise)

10. Timebase Generator Confirmation
A1 is should be OK
A2 is should be OK
B1 is should be OK
B2 is should be OK
PHASE is should be OK
PHAB is should be OK
SSP is should be OK
WRSTRB is should be OK
SSTOUT is should be OK

11. Pedestal (offset/baseline)
1 entry per 64-sample window, 512 windows
(32k storage cells/channel)

12. Pedestal (noise/RMS) Amplifiers OFF (2-3 ADC counts
~ 1-2mV) [only done on FMC – for reference]
Plot in bins of 512 windows
64 samples * 512 windows per channel (8 channels /ASIC)
Amplifiers ON
(6-8 ADC counts
~ 3-5mV)
[on Carrier]

13. CD-4 Independent Project Review
Timebase Alignment
FB_tap value optFB optValue
Found optimal FB at 110
 setting the optimal value..
Delay Lock Loop (DLL)
Feedback parameter
Adjust to minimize misalignment of 160MHz sine crossing 128-sample window boundary
June 1, 2016
CD-4 Independent Project Review 13

14. Fast Pulse Timing Verification
50%
CFD
50%
CFD
Interpolate between points to extract timing
ADC counts [~0.6mV/ADC]
Sample number [~0.368ns/sample]
June 1, 2016
CD-4 Independent Project Review 14

15. CD-4 Independent Project Review
Timing Verification
RMS of under <25ps>
per extracted timing edge
June 1, 2016
CD-4 Independent Project Review 15

16. Laser Calibration steps
Pedestal subtract
Correct Amplitude dependence
Run dT Minimizer, obtain results
Apply dT values
All binned, so easily implemented at Look-up tables on the SCROD FPGA
Both gain/efficiency and timing data taken at same time
About 8 hours per 128 channel board stack
June 1, 2016
CD-4 Independent Project Review 16

17. CD-4 Independent Project Review
1. Ped subtract & 50% CFD
Measure peak to determine 50% threshold
Before pedestal subtraction
Determine timing from interpolation
Default samples are ~ 0.37ns/point
June 1, 2016
CD-4 Independent Project Review 17

18. CD-4 Independent Project Review
1. After 50% CFD algorithm
No corrections applied
TDC assumed exactly 25ps/lsb
TDC INL not considered
Kinematic p.e. recoil tail
June 1, 2016
CD-4 Independent Project Review 18

19. CD-4 Independent Project Review
2. Voltage dependence
June 1, 2016
CD-4 Independent Project Review 19

20. CD-4 Independent Project Review
2. Improved Residual
June 1, 2016
CD-4 Independent Project Review 20

21. 2. TDC resolution residual
Differential and Integral non-linearity in sampling timebase (expected for these types of Switched Capacitor Array ASICs)
June 1, 2016
CD-4 Independent Project Review 21

22. 3. After Autocalibration
Compare with previous slide – timebase uniform and absolute timing calibrated (clock period closure constraint)
June 1, 2016
CD-4 Independent Project Review 22

23. Output After “dT minimizer” algorithm
Time between pulses in agreement,
No matter where look in the window
Absolute timebase cross-calibrated
With respect to SSTin clock period
June 1, 2016
CD-4 Independent Project Review 23

24. KPP Verification: single photon timing
1 entry per channel
Note: CAMAC TDC and phototube TTS contributions included: actual resolution is better
June 1, 2016
CD-4 Independent Project Review 24

25. KPP Verification: Event Time Zero
U. South Carolina
Tested (higher noise)
Hawaii
Tested
Spec
Obj
Thresh
June 1, 2016
CD-4 Independent Project Review 25

26. KPP Verification: Event Trigger Time
Note: Using coarser AXI clock during production testing.
4x faster clock (expect 4x improved resolution) in final trigger firmware [not yet ready]
Trigger time resolution [ns]
June 1, 2016
CD-4 Independent Project Review 26

27. Klm Baseline Scope 1288 16-channel waveform sampling ASICs 136 boards
June 1, 2016
CD-4 Independent Project Review 27

28. KLM Readout Baseline Scope
Benchtop testing 3 1 2 4 2
1) KLM Motherboard (136)
2) KLM Ribbon Header Interface Card [RHIC] (136)
3) KLM SCROD Rev A (136)
4) TARGETX Daughtercards (1288) 4
104 Barrel sets
32 Endcap 28
June 1, 2016
CD-4 Independent Project Review

29. Key Performance Parameters
132 9U MB + RHIC + SCROD + 10 DC sets
>21,000 channels
All channels tested with actual MPPCs
Tolerance
Threshold
Objective
Specification
Verification
136 Sets
Good Channels
90%
98%
99%
Trigger threshold, efficiency, gain, noise
100%
Deadtimeless Occupancy
0.5% 1% 2%
Throughput during calibration
2.5%
99% m.i.p. efficiency
10p.e.
7p.e.
6.5p.e.
Reduced size scintillator test stand (“SciFi”)
< 5 p.e.
Event Timing
10ns
5ns
2ns
40 MHz sine scan (SuperKEKB reference clock)
<0.1 ns
Event Trigger timing
20ns
Trigger timestamping during SciFi testing
8 ns
* 32 Barrel and 104 Endcap sets (+9 pre-production [usable] spares)
June 1, 2016
CD-4 Independent Project Review 29

30. KLM Acceptance Criteria
TargetX
Noise test, pedestal test
All samples, windows operational
Timing calibration for best performance
40MHz sine 600mVpp
Per chip scan of Delay Lock Loop feedback
Analog Front-end
MPPC bias test
Preamplifier carrier temperature readout
Trigger threshold scan
Waveform sampling triggered by MPPCs
Input noise
~2.25 mVrms
optimization
BEFORE
optimization
AFTER
June 1, 2016
CD-4 Independent Project Review 30

31. KLM Acceptance Testing
4x parallel Motherboard + DC test stations
Final RHIC test station with 2x Scintillating Fiber trackers
ASIC Pre-screened (ASIC check on MB) and bar-code entered 31
June 1, 2016
CD-4 Independent Project Review

32. KPP Verification: KLM Throughput
Because data flows through the RPC data concentrator,
Need to model throughput (queuing important)
June 1, 2016
CD-4 Independent Project Review 32

33. KPP Verification: Trigger Efficiency
Random readout – monitor trigger vs. amplitude
June 1, 2016
CD-4 Independent Project Review 33

34. KPP Verification: KLM Event Timing
Entries (per 25ps bin)
Zero-crossing timing determination
June 1, 2016
CD-4 Independent Project Review 34

35. KPP Verification: KLM Trigger Timing
Trigger time stamp offset for reconstructed pulses
June 1, 2016
CD-4 Independent Project Review 35

36. CD-4 Independent Project Review
backup
June 1, 2016
CD-4 Independent Project Review 36

37. IRSX Testing protocol overview
3,5 6 2 4 1 37
June 1, 2016
CD-4 Independent Project Review

38. CD-4 Independent Project Review
HV Testing
“Bare” HVB test fixture
Finished HVB test fixture
June 1, 2016
CD-4 Independent Project Review 38

39. PoGO pin installation Carrier Pogo pins soldered at PNNL
Completed
High Voltage Pogo pins soldered at Indiana U.
Pogo pin variation < 0.15mm  within acceptance 39