1. Interrupts In 8085 and 8086

2. Interrupts In 8085

3. what is Interrupt?
Interrupt is a mechanism by which an I/O or an instruction can suspend the normal execution of processor and get itself serviced. Generally, a particular task is assigned to that interrupt signal. In the microprocessor based system the interrupts are used for data transfer between the peripheral devices and the microprocessor.

4. Interrupt Service Routine(ISR)
A small program or a routine that when executed services the corresponding interrupting source is called as an ISR.

5. Maskable/Non-Maskable Interrupt
An interrupt that can be disabled by writing some instruction is known as Maskable Interrupt otherwise it is called Non-Maskable Interrupt. 

6. There are 6 pins available in 8085 for interrupt:
TRAP
RST 7.5
RST6.5
RST5.5
INTR
INTA

7. Execution of Interrupts
When there is an interrupt requests to the Microprocessor then after accepting the interrupts Microprocessor send the INTA (active low) signal to the peripheral. The vectored address of particular interrupt is stored in program counter. The processor executes an interrupt service routine (ISR) addressed in program counter. 

8. There are two types of interrupts used in 8085 Microprocessor:
Hardware Interrupts
Software Interrupts

9. Software Interrupts
A software interrupts is a particular instructions that can be inserted into the desired location in the program. There are eight Software interrupts in 8085 Microprocessor. From RST0 to RST7.
RST0
RST1
RST2
RST3
RST4
RST5
RST6
RST7

10. Hardware Interrupt
As i have already discussed that there are 6 interrupt pins in the microprocessor used as Hardware Interrrupts given below:
TRAP
RST7.5
RST6.5
RST5.5
INTR

11. Note:
INTA is not an interrupt. INTA is used by the Microprocessor for sending the acknowledgement. TRAP has highest priority and RST7.5 has second highest priority and so on.

12. The Vector address of these interrupts are given below
RST7.5
003CH
RST6.5
0034H
RST5.5
002CH
TRAP
0024H

13. TRAP
It is non maskable edge and level triggered interrupt. TRAP has the highest priority and vectores interrupt. Edge and level triggered means that the TRAP must go high and remain high until it is acknowledged. In case of sudden power failure, it executes a ISR and send the data from main memory to backup memory.  As we know that TRAP can not be masked but it can be delayed using HOLD signal. This interrupt transfers the microprocessor's control to location 0024H. 

14. RST7.5
It has the second highest priority. It is maskable and edge level triggered interrupt. The vector address of this interrupt is 003CH. Edge sensitive means input goes high and no need to maintain high state until it is recognized. 

15. RST6.5 and RST5.5
These are level triggered and maskable interrupts. When RST6.5 pin is at logic 1, INTE flip-flop is set. RST 6.5 has third highest priority and RST 5.5 has fourth highest priority.

16. INTR
It is level triggered and maskable interrupt. The following sequence of events occurs when INTR signal goes high:The 8085 checks the status of INTR signal during execution of each instruction.
If INTR signal is high, then 8085 complete its current instruction and sends active low interrupt acknowledge signal, if the interrupt is enabled.
On receiving the instruction, the 8085 save the address of next instruction on stack and execute received instruction.

17. Now Interrupts In 8086

18. INTR
Interrupt is the method of creating a temporary halt during program execution and allows peripheral devices to access the microprocessor. The microprocessor responds to that interrupt with an ISR (Interrupt Service Routine), which is a short program to instruct the microprocessor on how to handle the interrupt.

19. 8086 microprocessor −

20. Hardware Interrupts
Hardware interrupt is caused by any peripheral device by sending a signal through a specified pin to the microprocessor.
The 8086 has two hardware interrupt pins, i.e. NMI and INTR. NMI is a non-maskable interrupt and INTR is a maskable interrupt having lower priority. One more interrupt pin associated is INTA called interrupt acknowledge.

21. NMI
It is a single non-maskable interrupt pin (NMI) having higher priority than the maskable interrupt request pin (INTR)and it is of type 2 interrupt.
When this interrupt is activated, these actions take place −
Completes the current instruction that is in progress.
Pushes the Flag register values on to the stack.
Pushes the CS (code segment) value and IP (instruction pointer) value of the return address on to the stack.
IP is loaded from the contents of the word location 00008H.
CS is loaded from the contents of the next word location 0000AH.
Interrupt flag and trap flag are reset to 0.

22. INTR
The INTR is a maskable interrupt because the microprocessor will be interrupted only if interrupts are enabled using set interrupt flag instruction. It should not be enabled using clear interrupt Flag instruction.
The INTR interrupt is activated by an I/O port. If the interrupt is enabled and NMI is disabled, then the microprocessor first completes the current execution and sends ‘0’ on INTA pin twice. The first ‘0’ means INTA informs the external device to get ready and during the second ‘0’ the microprocessor receives the 8 bit, say X, from the programmable interrupt controller.

23. Software Interrupts INT- Interrupt instruction with type number
INT 3-Break Point Interrupt Instruction
INTO - Interrupt on overflow instruction

24. INT- Interrupt instruction with type number
It is 2-byte instruction. First byte provides the op-code and the second byte provides the interrupt type number. There are 256 interrupt types under this group.
Its execution includes the following steps −
Flag register value is pushed on to the stack.
CS value of the return address and IP value of the return address are pushed on to the stack.
IP is loaded from the contents of the word location ‘type number’ × 4
CS is loaded from the contents of the next word location.
Interrupt Flag and Trap Flag are reset to 0

25. INT- Interrupt instruction with type number
The starting address for type0 interrupt is H, for type1 interrupt is 00004H similarly for type2 is 00008H and ……so on. The first five pointers are dedicated interrupt pointers.
TYPE 0 interrupt represents division by zero situation.
TYPE 1 interrupt represents single-step execution during the debugging of a program.
TYPE 2 interrupt represents non-maskable NMI interrupt.
TYPE 3 interrupt represents break-point interrupt.
TYPE 4 interrupt represents overflow interrupt.
The interrupts from Type 5 to Type 31 are reserved for other advanced microprocessors, and interrupts from 32 to Type 255 are available for hardware and software interrupts.

26. INT 3-Break Point Interrupt Instruction
It is a 1-byte instruction having op-code is CCH. These instructions are inserted into the program so that when the processor reaches there, then it stops the normal execution of program and follows the break-point procedure.
Its execution includes the following steps −
Flag register value is pushed on to the stack.
CS value of the return address and IP value of the return address are pushed on to the stack.
IP is loaded from the contents of the word location 3×4 = 0000CH
CS is loaded from the contents of the next word location.
Interrupt Flag and Trap Flag are reset to 0

27. INTO - Interrupt on overflow instruction
It is a 1-byte instruction and their mnemonic INTO. The op-code for this instruction is CEH. As the name suggests it is a conditional interrupt instruction, i.e. it is active only when the overflow flag is set to 1 and branches to the interrupt handler whose interrupt type number is 4. If the overflow flag is reset then, the execution continues to the next instruction.
Its execution includes the following steps −
Flag register values are pushed on to the stack.
CS value of the return address and IP value of the return address are pushed on to the stack.
IP is loaded from the contents of word location 4×4 = 00010H
CS is loaded from the contents of the next word location.
Interrupt flag and Trap flag are reset to 0

28. Thanking you Pravin Janjal