1. Unit - 1 Interrupts M.Brindha AP/EIE

2. Unit - 1 Interrupts M.Brindha AP/EIE
When a microprocessor is interrupted, it stops executing its current program and calls a special routine which “services” the interrupt
The event that causes the interruption is called
Interrupt
The special routine executed to service the interrupt is called ISR - Interrupt Service Routine/Procedure
Unit - 1 Interrupts M.Brindha AP/EIE

3. Interrupt classification
Hardware Interrupt An interrupt caused by an “External signal ”
Software Interrupt An interrupt caused by “Special Instruction”
Maskable Interrupts Can be delayed or Rejected
Non-Maskable Interrupts Can not be delayed or Rejected
(Service must)
Vectored Where the subroutine starts is referred to as
Vector Location
Non-vectored  The address of the service routine needs to
be supplied externally by the device
Unit - 1 Interrupts M.Brindha AP/EIE

4. Unit - 1 Interrupts M.Brindha AP/EIE
8085
TRAP
RST7.5
RST6.5
RST 5.5
INTR
INTA
The ‘EI’ instruction is a one byte instruction and is used to Enable the non-maskable interrupts.
The ‘DI’ instruction is a one byte instruction and is used to Disable the non-maskable interrupts.
Unit - 1 Interrupts M.Brindha AP/EIE

5. Unit - 1 Interrupts M.Brindha AP/EIE
Interrupt Name
Maskable
Vectored
INTR
Yes No
RST 5.5
RST 6.5
RST 7.5
TRAP
Unit - 1 Interrupts M.Brindha AP/EIE

6. Interrupt Vectors & the Vector Table
An interrupt vector is a pointer to where the ISR is stored in memory.
All interrupts (vectored or otherwise) are mapped onto a memory area called the Interrupt Vector Table (IVT).
The IVT is usually located in (0000H - 00FFH).
Vector Address = Interrupt number * 8
Unit - 1 Interrupts M.Brindha AP/EIE

7. Unit - 1 Interrupts M.Brindha AP/EIE
Interrupt Name
Calculation
Vector Address
INTR --
TRAP ( RST 4.5)
4.5x8=36
0024H
RST 5.5
5.5x8=44
002CH
RST 6.5
6.5x8=52
0034H
RST 7.5
7.5x8=60
003CH
Unit - 1 Interrupts M.Brindha AP/EIE

8. 8085 Interrupts Summary Interrupt Name Triggering Method Priority
Maskable
Masking Method
Vector Address
TRAP
RST 4.5
Edge & Level Sensitive
1st Highest No
None
0024H
RST 7.5
Edge Sensitive
2nd
Yes
DI / EI
SIM
003CH
RST 6.5
Level Sensitive
3rd
0034H
RST 5.5
4th
002CH
INTR
5th
Lowest
Pin
( INTR & INTA) --

9. Unit - 1 Interrupts M.Brindha AP/EIE
Software Interrupt
The 8085 recognizes 8 RESTART instructions:
RST n ( RST0 - RST7)
Each of these would send the execution to a redetermined hard-wired memory location:
Restart Instruction
Vector Address
RST 0
CALL 0000H
RST 1
CALL 0008H
RST 2
CALL 0010H
RST 3
CALL 0018H
RST 4
CALL 0020H
RST 5
CALL 0028H
RST 6
CALL 0030H
RST 7
CALL 0038H
Unit - 1 Interrupts M.Brindha AP/EIE

10. The 8085 Maskable/Vectored Interrupt Process
The interrupt process should be enabled using the EI instruction.
The 8085 checks for an interrupt during the execution of every instruction.
If there is an interrupt, and if the interrupt is enabled using the interrupt mask, the microprocessor will complete the executing instruction, and reset the interrupt flip flop.
The microprocessor then executes a call instruction that sends the execution to the appropriate location in the interrupt vector table.
Unit - 1 Interrupts M.Brindha AP/EIE

11. The 8085 Maskable/Vectored Interrupt Process
When the microprocessor executes the call instruction, it saves the address of the next instruction on the stack.
The microprocessor jumps to the specific service routine.
The service routine must include the instruction EI to re-enable the interrupt process.
At the end of the service routine, the RET instruction returns the execution to where the program was interrupted.
Unit - 1 Interrupts M.Brindha AP/EIE

12. SIM value must be loaded in Accumulator
SIM – Serial interrupt mask
SDO
SDE
XXX
R7.5
MSE
M7.5
M6.5
M5.5 1 2 3 4 5 6 7
RST5.5 Mask }
0 - Available
1 - Masked
Serial Data Out
Either 0 or 1
RST6.5 Mask
RST7.5 Mask
Enable Serial Data
0 - Disable
1 - Enable
Mask Set Enable
0 - Ignore bits 0-2
1 - Set the masks according
to bits 0-2
Not Used
Force RST7.5 Flip Flop to reset
SIM value must be loaded in Accumulator
Unit - 1 Interrupts M.Brindha AP/EIE

13. Unit - 1 Interrupts M.Brindha AP/EIE
Example
MSE Mask Set Enable
RST 6.5 Mask
RST 5.5 & 7.2 Unmask
RST FF Don’t Reset
Serial Data Igonered
SDO
SDE
XXX
R7.5
MSE
M7.5
M6.5
M5.5 1 1
Contents of accumulator are: 0AH
EI ; Enable interrupts including INTR
MVI A, 0A ; Prepare the mask to enable RST 7.5, and 5.5, disable 6.5
SIM ; Apply the settings RST masks
Unit - 1 Interrupts M.Brindha AP/EIE

14. Unit - 1 Interrupts M.Brindha AP/EIE
Example
MSE Mask Set Disable
RST FF Reset
Serial Data Enable
Serial Data output is 0
SDO
SDE
XXX
R7.5
MSE
M7.5
M6.5
M5.5 1 1 1
Contents of accumulator are: 54H
Unit - 1 Interrupts M.Brindha AP/EIE

15. } Rim – read interrupt mask
SDI
P7.5
P6.5
P5.5 IE
M7.5
M6.5
M5.5 1 2 3 4 5 6 7
RST5.5 Mask }
0 - Available
1 - Masked
Serial Data In
RST6.5 Mask
RST7.5 Mask
RST5.5 Interrupt Pending
RST6.5 Interrupt Pending
Interrupt Enable
Value of the Interrupt Enable
Flip Flop
RST7.5 Interrupt Pending
Set – 1
Reset - 0
Copies the status of the interrupts into the accumulator
Unit - 1 Interrupts M.Brindha AP/EIE

16. Unit - 1 Interrupts M.Brindha AP/EIE
Example
Interrupt Enable
RST 5.5 & 6.5 Masked
RST 7.5 Pending
Serial Input Data is 0
SID
P7.5
P6.5
P5.5 IE
M7.5
M6.5
M5.5 1 1 1 1
Contents of accumulator are: 4BH
Unit - 1 Interrupts M.Brindha AP/EIE