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Physics & Astronomy HEP Electronics

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Presentation on theme: "Physics & Astronomy HEP Electronics"— Presentation transcript:

1 Physics & Astronomy HEP Electronics
TTCrm versus TTCrq ATLAS SCT/Pixel TIM FDR/PRR 28 June 2004 John Lane, Martin Postranecky, Matthew Warren 28 June 2004 ATLAS SCT/Pixel TIM FDR/PRR Martin Postranecky: TTCrm/TTCrq

2 ATLAS SCT/Pixel TIM FDR/PRR Martin Postranecky: TTCrm/TTCrq
Originally selected as the TTCrx mezzanine board to be used on TIM-3 Uses 2 connectors J1 and J2 Just fits on single-width board But last year reported : Potential Phase Shift of the clock output of up to 400 ps, depending on the activity on the commands channel B Potential increased clock jitter up to ps RMS on the TTCrm clock outputs 28 June 2004 ATLAS SCT/Pixel TIM FDR/PRR Martin Postranecky: TTCrm/TTCrq

3 ATLAS SCT/Pixel TIM FDR/PRR Martin Postranecky: TTCrm/TTCrq
Additional QPLL reduces this potential jitter from TTCrx chip to about 50 ps peak-to-peak QPLL has narrow locking range of +/- 3.7 kHz around MHz ( < +/-100 ppm ) TTCrq board requires one additional connector J3 for the QPLL inputs/outputs ( in addition to the J1 & J2 ) 7mm tall spacers on all connectors required for backward compatibility with TTCrm Ref : 28 June 2004 ATLAS SCT/Pixel TIM FDR/PRR Martin Postranecky: TTCrm/TTCrq

4 ATLAS SCT/Pixel TIM FDR/PRR Martin Postranecky: TTCrm/TTCrq
TTCrm versus TTCrq J3 ( top ) J1 ( below ) J2 ( below ) J2 ( top ) J1 ( top ) TTCrm TTCrq 28 June 2004 ATLAS SCT/Pixel TIM FDR/PRR Martin Postranecky: TTCrm/TTCrq

5 ATLAS SCT/Pixel TIM FDR/PRR Martin Postranecky: TTCrm/TTCrq
TTCrm versus TTCrq 28 June 2004 ATLAS SCT/Pixel TIM FDR/PRR Martin Postranecky: TTCrm/TTCrq

6 TTCrm CLOCK JITTER OBSERVED :
Up to 400 ps peak-to-peak on CLOCK40DES1 output pin J1 pin 2 Phase shift of clock seen when running with continuous L1A triggers NOTE : Jitter on CLOCK40DES1 on J1 pin 2, triggering on the raising edge of clock, at about +1V trigger threshold, and about 10 usec ( = 400 clocks ) from trigger point Scope set to infinite persistence 28 June 2004 ATLAS SCT/Pixel TIM FDR/PRR Martin Postranecky: TTCrm/TTCrq

7 ATLAS SCT/Pixel TIM FDR/PRR Martin Postranecky: TTCrm/TTCrq
TTCrm Clock Jitter CLOCK40DES1 Trig. not running 200pS/div Delay 10uS Jitter ~ 400pS p-p 28 June 2004 ATLAS SCT/Pixel TIM FDR/PRR Martin Postranecky: TTCrm/TTCrq

8 ATLAS SCT/Pixel TIM FDR/PRR Martin Postranecky: TTCrm/TTCrq
TTCrm Clock Jitter CLOCK40DES1 Trigger running 4.0nS/div Delay 10uS Clock Phase Shift 28 June 2004 ATLAS SCT/Pixel TIM FDR/PRR Martin Postranecky: TTCrm/TTCrq

9 ATLAS SCT/Pixel TIM FDR/PRR Martin Postranecky: TTCrm/TTCrq
TTCrm Clock Jitter CLOCK40DES1 Trigger running 200pS/div Delay 10uS Jitter ~400pS p-p Clock Phase Shift 28 June 2004 ATLAS SCT/Pixel TIM FDR/PRR Martin Postranecky: TTCrm/TTCrq

10 TTCrq CLOCK JITTER OBSERVED :
Up to 200 ps peak-to-peak on CLOCK40DES1 output pin ( with QPLL selected and locked ) When running with continuous L1A triggers, the QPLL looses lock repeatedly ( about once every 15 triggers received ) NOTE : The TTCrq module used in these tests was an untested sample on loan to UCL. Our clock runs at MHz, which should be inside the locking range 28 June 2004 ATLAS SCT/Pixel TIM FDR/PRR Martin Postranecky: TTCrm/TTCrq

11 ATLAS SCT/Pixel TIM FDR/PRR Martin Postranecky: TTCrm/TTCrq
TTCrq Clock Jitter CLOCK40DES1 500pS/div Delay 10uSec Jitter ~ 200pS p-p 28 June 2004 ATLAS SCT/Pixel TIM FDR/PRR Martin Postranecky: TTCrm/TTCrq

12 TTCrq – Jitter on Backplane
PCLKB output 500pS/div Delay = 10uSec Jitter ~ 300pS p-p 28 June 2004 ATLAS SCT/Pixel TIM FDR/PRR Martin Postranecky: TTCrm/TTCrq

13 ATLAS SCT/Pixel TIM FDR/PRR Martin Postranecky: TTCrm/TTCrq
Clock Delay CLOCK40DES1 PCLKB Delay ~ 8nS 28 June 2004 ATLAS SCT/Pixel TIM FDR/PRR Martin Postranecky: TTCrm/TTCrq

14 ATLAS SCT/Pixel TIM FDR/PRR Martin Postranecky: TTCrm/TTCrq
CONCLUSION : TIM-3B modified so that it will accept and run with either TTCrm or TTCrq. All additional inputs and outputs on TTCrq connector J3 are connected to FPGA-2 to allow control and use of QPLL if required Extra 7mm tall spacers required on all TTCrq connector pins for backward compatibility to TTCrm 28 June 2004 ATLAS SCT/Pixel TIM FDR/PRR Martin Postranecky: TTCrm/TTCrq

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