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Graphics on GPU © David Kirk/NVIDIA and Wen-mei W. Hwu, 2007-2010
ECE408, University of Illinois, Urbana-Champaign
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Graphics Pipeline Process objects one at a time in the order they are generated by the application Can consider only local lighting Pipeline architecture All steps can be implemented in hardware on the graphics card display E. Angel and D. Shreiner: Interactive Computer Graphics 6E © Addison-Wesley 2012
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Texture Mapping Example
Texture mapping example: painting a world map texture image onto a globe object. © David Kirk/NVIDIA and Wen-mei W. Hwu, ECE408, University of Illinois, Urbana-Champaign
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OpenGL Architecture geometry pipeline CPU Immediate Mode Per Vertex
Operations & Primitive Assembly Polynomial Evaluator Display List Per Fragment Operations Frame Buffer CPU Rasterization Texture Memory Pixel Operations Angel: Interactive Computer Graphics 5E © Addison-Wesley 2009
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A Fixed Function GPU Pipeline
Host CPU Host Interface GPU Vertex Control A Fixed Function GPU Pipeline Vertex Cache VS/T&L Triangle Setup Raster Frame Buffer Memory Texture Cache Shader ROP © David Kirk/NVIDIA and Wen-mei W. Hwu, ECE408, University of Illinois, Urbana-Champaign FBI
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Programmable Vertex and Pixel Processors
3D Application or Game 3D API Commands CPU 3D API: OpenGL or Direct3D CPU – GPU Boundary GPU Command & Data Stream GPU Assembled Polygons, Lines, and Points Pixel Location Stream Vertex Index Stream Pixel Updates GPU Front End Primitive Assembly Rasterization & Interpolation Raster Operations Framebuffer Pre-transformed Vertices Rasterized Pre-transformed Fragments Transformed Vertices Transformed Fragments Programmable Vertex Processor Programmable Fragment Processor An example of separate vertex processor and fragment processor in a programmable graphics pipeline © David Kirk/NVIDIA and Wen-mei W. Hwu, ECE408, University of Illinois, Urbana-Champaign
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Unified Graphics Pipeline
FB SP L1 TF Thread Processor Vtx Thread Issue Setup / Rstr / ZCull Geom Thread Issue Pixel Thread Issue Data Assembler Host © David Kirk/NVIDIA and Wen-mei W. Hwu, ECE408, University of Illinois, Urbana-Champaign
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CPU GPU "Host" Points: main() Colours: Id: Memoy(data): H.W CPU Code
x y z ...... main() Colours: r g b ...... Id: 1 2 ...... GPU Memoy(data): x y z ...... r g b H.W CPU Code Vertex shader Pixel shader Identified table Id Name Location 1 Vsource 2 Vobj 3 Vposition 4 Vcolour 5 Psource 6 Pobj main()...... © David Kirk/NVIDIA and Wen-mei W. Hwu, ECE408, University of Illinois, Urbana-Champaign © David Kirk/NVIDIA and Wen-mei W. Hwu, ECE408, University of Illinois, Urbana-Champaign 8
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