14. Refer example 2.4on page 64 ACA(Kai Hwang)
And refer another ppt attached for static scheduling example.

18. Bisection width b = minimum number of edges cut to split a network into two parts each having the same number of nodes.

25. Factors Affecting Network Performance
Functionality – how the network supports data routing, interrupt handling, synchronization, request/message combining, and coherence
Network latency – worst-case time for a unit message to be transferred
Bandwidth – maximum data rate
Hardware complexity – implementation costs for wire, logic, switches, connectors, etc.
Scalability – how easily does the scheme adapt to an increasing number of processors,memories, etc

36. A fat tree network of 16 processing nodes.

70. Different classes of Multistage Interconnection Networks(MINs) differ in switch module and in the kind of interstage pattern used.
The patterns often include perfect shuffle,butterfly,crossbar,cube connection etc

71. Omega Network A 2  2 switch can be configured for
Straight-through
Crossover
Upper broadcast (upper input to both outputs)
Lower broadcast (lower input to both outputs)
(No output is a somewhat vacuous possibility as well)
With four stages of eight 2  2 switches, and a static perfect shuffle for each of the four ISCs, a 16 by 16 Omega network can be constructed (but not all permutations are possible).
In general , an n-input Omega network requires log 2 n stages of 2  2 switches and n / 2 switch modules.

72. Patterns

73. 16 x 16 omega network

74. Network Topologies: Multistage Omega Network
A complete Omega network with the perfect shuffle interconnects and switches can now be illustrated:
A complete omega network connecting eight inputs and eight outputs.
An omega network has p/2 × log p switching nodes, and the cost of such a network grows as (p log p).

75. Network Topologies: Multistage Omega Network – Routing
An example of blocking in omega network: one of the messages
(010 to 111 or 110 to 100) is blocked at link AB.

77. Recursive Construction
The first stage contains one NXN block and second stage contains 2 (N/2)x (N/2) sub blocks labeled Co and C1.
This construction can be recursively repeated to bub block until 2x2 switch is reached.

78. 7/19/2018
Baseline Network
The figure to the right shows an 8 x 8 Baseline network. A C B D 1 2 3 4 5 6 7 A C B D J I E G
To generalize into an n x n Baseline network, first create one stage of (n / 2) 2 x 2 switches.
Then one output from each 2 x 2 switch is connected to an input of each (n / 2) x (n / 2) switch. K L H F
Then the (n / 2) x (n / 2) switches are replaced by (n / 2) x (n / 2) Baseline networks constructed in the same way.
The Baseline and Omega networks are isomorphic with each other.

79. Isomorphism Between Baseline and Omega Networks (cont.)
7/19/2018
Isomorphism Between Baseline and Omega Networks (cont.)
Starting with the Baseline network.
If B and C, and F and G are repositioned while keeping the fixed links as the switches are moved. A D 1 2 3 4 5 6 7 I E L H C B J K F G B C J F K G
The Baseline network transforms into the Omega network.
Therefore, the Baseline and Omega networks are isomorphic.

81. Crossbar Networks
A crossbar network can be visualized as a single-stage switch network.
Like a telephone switch board, the crosspoint switches provide dynamic connections between(source, destination) pairs.
Each cross point switch can provide a dedicated connection path between a pair.
The switch can be set on or off dynamically upon program demand.

82. Shared Memory Crossbar
To build a shared-memory multiprocessor, one can use a crossbar network between the processors and memory modules (Fig. 2.26a).
The C.mmp multiprocessor has implemented a 16 x 16 crossbar network which connects 16 PDP 11 processors to 16 memory modules, each of which has a capability of 1 million words of memory cells.

83. Shared Memory Crossbar Switch

84. Shared Memory Crossbar Switch
Note that each memory module can satisfy only one processor request at a time.
When multiple requests arrive at the same memory module simaltaneously,cross bar must resolve the conflicts.

85. Interprocess Communication Crossbar Switch
This large crossbar was actually built in vector parallel processor.
The PEs are the processor with attached memory.
The CPs stand for control processor which are used to supervise entire system operation.

86. Interprocess Communication Crossbar Switch

87. End Of Module 5