1. Front-end electronics Bis7-8
R.Cardarelli
Chios 26/09/2016

2. Status front-end electronic of bis7-8
Tests amplifier + discriminator, done. Small problem for driver
Tests Faraday cage, done
Realization by IHP of the first 600 discriminator chips, in progress
Design of printed board front-end and back-end, in progress
Design of services front-end, in progress
Design of prototype N°-1 Bis7-8 in progress
20/09/2016

3. BIS78 prototype-0 implementation
Amp is done
Discriminator is done
Printed board in progress 1 8
discri
HP TDC
GOL
Serial out
Amp
04/02/2015
R. Cardarelli, SSC 2015

4. Amp
Dis
IN 1
IN 2
IN 3
OUT 1
OUT 2
OUT 3
Amplifier
Amplification
0.5mV/fC
Noise
1000 e- RMS
Power BW
40MHz
Pulse Width
30 ns
Rise time
> 300 ps
Discriminator
Vth
0.5 mV
Max freq
100MHz
Out
LVTTL
Si standard component
SiGe full custom
3-5 Volt 1–2 mA
2-3 Volt mA

5. Front end connection to the HPTDC+GOL
+3V
We choose single ended LV TTL logic for the connection between FE and HPTDC
The motivation is:
Minimize the driver consumption (benefits both FE and HPTDC)
Simple and robust against noise
Pull up resistor
Open collector TTL
Transmission line
HP TDC
GND
04/02/2015
R. Cardarelli, SSC 2015

7. Faraday cage and layout of Bis 7-8

8. Time schedule 2016 2017 2018 Discriminator prototype First 2400 ch
Discriminator prototype
First 2400 ch
Full ch
Printed board prototype

9. conclusions The tests of discriminator is done
The tests of amplifier is done
The tests of discriminator + amplifier is done
The printed board is in progress
The front-end of the Bis7-8 is in progress according the time schedule

10. Discriminator
The discriminator design is based on SG25H3 technology from IHP (SiGe Bi-CMOS technology).
The schematic is ready, the layout is in progress.
A multi-project run is foreseen by the end of the year.
The power consumption is 8.3 mW/channel, with 2V LV power supply.
The following simulations are shown for a triangular input voltage pulse of 500 ps rise time, 10 ns fall time.
𝑓 𝑡 =110 𝐺𝐻𝑧 𝛽=150

11. Development of the new full custom Front End in SiGe technology
Chip schematic layout
04/02/2015
R. Cardarelli, SSC 2015

12. High performance discriminator SiGe technology
Sensitivity
Max frequency
Power consumption
Charge to Time
(time over threshold)
< 4mV
>1 GHz
1-3 mW
log (out) 8 bit dynamics
Limiting amplifier
Digital buffer
04/02/2015
R. Cardarelli, SSC 2015

13. Discriminator
From the zoomed view, a total time jitter of 300 ps can be observed.

14. The RPC electronics for phase 2 applications
How to scale the RPC performance by a factor >10?
The timing and the signal occupancy is already very low, the problem concerns the operating current
Moving the amplification from the gas to the FE allows to increase the rate capability correspondingly.
A narrower gas gap optimizes the charge distribution and produce faster signals
Under this condition the present ATLAS RPC ageing tests would be valid for higher rates
04/02/2015
R. Cardarelli, SSC 2015

15. Rate capability issues
As in most detectors with resistive electrodes, the RPC counting rate capability is limited by the voltage drop on resistive electrodes.
𝑉 𝑔𝑎𝑠 = 𝑉 𝐴 −𝑅∙𝐼= 𝑉 𝐴 −𝜌∙𝑑∙ 𝑄 ∙Φ
Reduce resistivity
Reduce average charge/avalanche. Extends the rate capability at constant working current.
Reduce electrode thickness
This problem was addressed by introducing the new charge amplifier, in order to transfer part of the amplification from the gas to the Front End electronics.
04/02/2015
R. Cardarelli, SSC 2015

16. SiGe amplifier application on Resistive Plate Chambers (1)
A 1 mm gap RPC detector read out with a ATLAS like threshold (black), the new preamplifier in silicon technology (blue) and in SiGe technology (red)
Data from a cosmic ray test.
Using a more sensitive front end allows to operate the detector at a lower gas gain.
Total delivered charge per count in the detector. The working point with different front ends is reported.
ATLAS like threshold
Silicon new preamplifier
SiGe new preamplifier
Data from a cosmic ray test.
Lower gain means lower charge per count.
NOTE: the total charge reported is not the prompt charge collected in the front end.
04/02/2015
R. Cardarelli, SSC 2015

17. SiGe amplifier application on Resistive Plate Chambers (2)
Operating the detector at a lower charge per count means improving rate and reducing the ageing of the detector.
Efficiency vs counting rate simulated for a 1mm single gap RPCs.
ATLAS like threshold
Silicon new preamplifier
SiGe new preamplifier
Starting from experimental data at 7 KHz/cm2 we simulated the efficiency VS counting rate for a RPCs with ATLAS standard electrode plates. The applied voltage is 200 V above the plateau knee. The results are in agreement with the experimental data collected at the CERN GIF.
04/02/2015
R. Cardarelli, SSC 2015

18. Space resolution of the RPC with the charge centroid method
The residues distribution between the first two RPCs has a jitter of 187±7 𝜇𝑚.
This corresponds to a space resolution of 𝟏𝟑𝟐±𝟓 𝝁𝒎 for each detector, compatible with the expectations from the readout contribution.
An upper limit for RPC intrinsic space resolution can be set to
𝜎 𝑆,𝑖𝑛𝑡𝑟𝑖𝑛𝑠𝑖𝑐 = 𝜎 𝑆 2 − 𝜎 𝑆,𝐹𝐸 2 ≲70−80 𝜇𝑚
04/02/2015
R. Cardarelli, SSC 2015

19. Combined diamond-RPC timing
Assuming σcomb2= σDiam2 + σRPC2
For orthogonal orientation the overall jitter is dominated by the diamond
σComb = 1 ns
For parallel orientation the jitter is dominated by the RPC
σComb ≈ σRPC = 0.41 ns
04/02/2015
R. Cardarelli, SSC 2015

20. Block diagram and performance of a new full custom front-end Si-Ge chip
IN 1
IN 8
Analog out
Digital out
Serial out (10 Gbit/sec)
PLL
counter
Latch
Sinc in
Discr. CK
I/O
04/02/2015
R. Cardarelli, SSC 2015

21. First iteration results
Bench test of the first multi-project run shown that the simulation is in agreement with the experimental data.
We highlighted the following open problems:
Reliability  some channel failures occurred in specific circumstances
Output driver  we need to implement a low consumption driverization, compatible with the requested digital output standard
04/02/2015
R. Cardarelli, SSC 2015

22. Precision time digitization with SiGe technology
Exploit the properties of state of the art SiGe transistors to produce 10 ps TDC.
SiGe HBT technology: transistor performance
𝑓 𝑡 =0.25 𝑇𝐻𝑧
𝑓 𝑚𝑎𝑥 =0.3 𝑇𝐻𝑧
𝛽=900
Few picosecond buffer delay.
Delay precision of the order of ~100 fs.
>20 𝐺𝐻𝑧 oscillation frequency can be easily achieved.
Small dynamic range required for PET scanners.
10 ps binning TDC with 4 ps resolution with very simple schematics can be designed.

23. Phase 2 Front end proposed solution
IN 1
IN 8
Wide band serial out
PLL
counter
Latch
Sinc in
Discr. CK
I/O OR
8 channels digital OR
04/02/2015
R. Cardarelli, SSC 2015

24. Phase 2 Front End final design
The final design of the phase 2 front end will depend on the results of the BIS78 electronics, concerning the following points:
Position of the FE PCB in or out of the RPC Farady cage. (Noise rejection vs. accessibility)
Separate or not the analog and digital part (as for the BIS78)
Optimization of the channels per chip
Optimization of the FE parameters with respect to the RPC gap final layout
04/02/2015
R. Cardarelli, SSC 2015

25. Conclusions
The R&D is now aimed to produce the BIS78 module-0 by the end of 2016
The BIS78 results have a crucial impact for the Phase2 design
The BIS78 intensive R&D program is clearly justified by the phase 2 RPC upgrade proposal
All the simulation and tests make us very confident that the proposed solution is fully compliant with the Phase 2 requirements
04/02/2015
R. Cardarelli, SSC 2015

26. Front end connection to the HPTDC+GOL
+3V
We choose single ended LV TTL logic for the connection between FE and HPTDC
The motivation is:
Minimize the driver consumption (benefits both FE and HPTDC)
Simple and robust against noise
Pull up resistor
Open collector TTL
Transmission line
HP TDC
GND
04/02/2015
R. Cardarelli, SSC 2015

27. Conclusions
The R&D is now aimed to produce the BIS78 module-0 by the end of 2016
The BIS78 results have a crucial impact for the Phase2 design
The BIS78 intensive R&D program is clearly justified by the phase 2 RPC upgrade proposal
HP TDC FPGA TDC ?
04/02/2015
R. Cardarelli, SSC 2015

28. First simulation results with SiGe technology
200 ps
Phase delay: 13 ps.
Delay precision: 100 fs.
Time measurement precision: σ≅4 ps.

29. Motivation for a new Front-end design
For a reliable RPC system working in the IB for Phase 2 it is mandatory to increase the performance of the front-end
The existing amplifiers are not optimized for fast pulse operation at the required level of performance < 1000 e noise, wide dynamic range and low sensitivity to coupling capacitance noise
Decrease the noise for short shaping (problem of the signal overlapping at high rate)
Decrease the rise time (for real time TOF capability)
Increase the performance of the discriminator and the Time-Digital Converter
Minimize the complexity (high reliability)
Minimize the cost
Minimize power consumption
Rad-Hard technology (1 Mrad)
All this requirements can be satisfied by a custom design in BiCMOS SiGe technology
04/02/2015
R. Cardarelli, SSC 2015