1. Munigala Srinivaas EE-587 (April 22 2008)
USRP
Munigala Srinivaas
EE-587 (April )

2. Communication model Antenna — RF front end — ADC — software code
RF front end – Low noise amplifier, LPF, mixer
ADC USRP
software code– GNU radio
MUNIGALA SRINIVAAS

3. GNU RADIO Extensive toolkit of basic processing blocks:
FIR, IIR and FFT filters
Filter coefficient generators: HP, LP, BP
Signal generators
Basic math operations
FFTs
Modulators, Demodulators, PLLs, etc
Signal sources and Sinks
Tied together with Python
Blocks written in C++
MUNIGALA SRINIVAAS

4. USRP Software needs method for getting digitized signals in/out of PC
USRP has emerged as standard way of dealing with RF from DC up to 2.4Ghz: daughter-cards act as up and down converters
64Msps A/D and D/A
FPGA for various functions
Decimation, half-band filtering, etc
Digital Down converter
USB2.0 Interface to PC using FX2 (8051) uC
MUNIGALA SRINIVAAS

5. USRP
MUNIGALA SRINIVAAS

6. USRP It consists of Four high-speed analog-to-digital converters
Four high-speed digital-to-analog converters
An FPGA
Glue logic
MUNIGALA SRINIVAAS

7. Block Diagram of USRP
MUNIGALA SRINIVAAS

8. BLOCK DIAGRAM
MUNIGALA SRINIVAAS

9. Digital down-conversion and decimation
MUNIGALA SRINIVAAS

10. Digital up-conversion
MUNIGALA SRINIVAAS

11. FPGA Features of the EP1C12 Series Cyclone™ LEs 12,060
M4k RAM blocks (128 x 36 bits) 52
Total RAM bits 239,616
PLLs 2
Maximum user I/O pins 173
Operating Temperature 0°C ~ 85°C
MUNIGALA SRINIVAAS

12. References http://gnuradio.org/trac/wiki/UsrpRfxDiagrams
MUNIGALA SRINIVAAS