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New Product Introduction: 4Mb Asynchronous SRAM with ECC ECC = Error-Correcting Code High-Speed, Low-Power Asynchronous SRAMs With On-Chip ECC to Improve.

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Presentation on theme: "New Product Introduction: 4Mb Asynchronous SRAM with ECC ECC = Error-Correcting Code High-Speed, Low-Power Asynchronous SRAMs With On-Chip ECC to Improve."— Presentation transcript:

1 New Product Introduction: 4Mb Asynchronous SRAM with ECC ECC = Error-Correcting Code
High-Speed, Low-Power Asynchronous SRAMs With On-Chip ECC to Improve Reliability 1,000-Fold

2 Modern Systems Need Ultra-Reliable SRAMs
Modern systems cannot tolerate bit errors in SRAMs Cosmic background radiation causes unavoidable bit errors in SRAMs at a low rate Advanced computing systems require ultra-reliable high-speed SRAMs as configuration memories1 Battery-backed systems require ultra-reliable low-power SRAMs to store critical data for a long time Thus error detection and correction in SRAMs is required for critical applications Programmable Logic Controller by Siemens Router by Cisco Multi-Function Printer by Canon Cypress is a market leader in the Asynchronous SRAM space, and offers the broadest portfolio of fast asynchronous and low-power asynchronous SRAM (MoBL™) devices. Asynchronous SRAMs are used in a wide variety of industrial, medical, commercial, automotive and military applications that require the highest standards of reliability and performance. Best-in class process technology and manufacturing; steadfast customer support; and high quality design ensure that Cypress asynchronous SRAM devices meet and exceed expectations. Cypress continues to invest into SRAM technology to create new and innovative products even as a number of manufacturers have exited the space. Soft Errors2 result in malfunction due to corrupted configuration information Soft Errors result in malfunction due to corrupted configuration information Soft Errors result in faulty configuration and status information Modern systems require ultra-reliable, high-performance SRAMs with Error-Correcting Code (ECC) 1 A memory device used to load system configuration registers at boot-up time in which a single-bit error can cause a system crash 2 Bit errors caused by cosmic background radiation 3a

3 Cypress Is the SRAM Market Leader
Cypress is the world’s largest and most experienced Asynchronous SRAM supplier Has >40% market share Supplied 10 generations of Asynchronous SRAMs Invests more in R&D than any other competitor Cypress has the broadest Asynchronous SRAM portfolio and offers: 600 Asynchronous SRAMs Fast Asynchronous SRAMs from 64Kb to 32Mb Low-power (MoBL®) SRAMs with densities from 64Kb to 64Mb Products in industrial, automotive and rad-hard grades Ultra-Reliable SRAMs with on-chip ECC for single-bit error detection and correction Cypress is the most dependable Asynchronous SRAM supplier and offers: Lead times of ≤5 weeks, with ≥99.4% on-time delivery Multiple qualified fabs, assembly sites and test sites Legacy product support up to 20 years Cypress introduces three new Ultra-Reliable 4Mb Asynchronous SRAMs with on-chip ECC that are 1,000x more reliable than standard SRAMs without ECC 3b

4 Terms You Will Hear Today
Asynchronous SRAM An SRAM device in which read or write operations do not require an external clock Fast SRAM High-speed Asynchronous SRAMs with an access time of ≤20 ns More Battery Life (MoBL®) SRAM Low-power Asynchronous SRAMs with ≤2.5-µA/Mb standby current PowerSnooze™ SRAM Fast SRAM with an additional power-saving mode with ≤4-µA/Mb deep-sleep current Ultra-Reliable SRAM An SRAM with a SER of <0.1 FIT/Mb Soft Error A bit error caused by cosmic background radiation Soft Error Rate (SER) The rate at which a device is predicted to have Soft Errors Failure-in-Time (FIT) A reliability measure of the projected failure rate of a device One FIT/Mb equals one projected bit failure per Mb over one billion hours of device operation Error-Correcting Code (ECC) Data encoded with extra “parity” bits to detect and correct bit errors ERR Pin A status pin on Cypress Asynchronous SRAMs with on-chip ECC that indicates the occurrence of single-bit errors 4

5 Design Problems Engineers Face
FIT rates of <10 FIT/Mb are unachievable in standard SRAMs without ECC Today's standard SRAMs have FIT rates in the range of 150-1,500 FIT/Mb Correcting Soft Errors with system-level ECC solutions forces undesirable system design trade-offs System-level ECC solutions increase design complexity and cycle time They also require additional memory and error-correction chips, increasing board space and cost Modern systems require memories with fast access time and low standby current A typical 4Mb high-speed SRAM with a 10-ns access time consumes a high 10-mA standby current A typical 4Mb low-power SRAM with an 8-µA standby current has a slow access time of 45 ns Cypress 4Mb Asynchronous SRAM with ECC solves these problems with: A FIT rate of <0.1 FIT/Mb A single-chip solution with on-chip ECC that reduces board space, cost and design complexity A 10-ns access time and 15-µA deep-sleep current (PowerSnooze SRAM)  Cypress’s 4Mb Ultra-Reliable Asynchronous SRAMs provide both high speed and low power 5

6 Cypress 4Mb Asynchronous SRAM vs. Competition’s
High-Speed SRAM Features CY7x1041xx IS61/64WVxx R1RW/P04xx On-Chip ECC Yes No Soft Error Rate <0.1 FIT/Mb <0.5 FIT/Mb1 >150 FIT/Mb Voltage Range V V V Access Time (Max.) 10 ns 8 ns Operating Current 45 mA 35 mA 115 mA Data Retention Voltage (Min.) 1.0 V 2.0 V Standby Current (Max.) 15 µA2 6,000 µA 5,000 µA Low-Power SRAM Features CY6214xx IS62/65WVxx RM/1LV/P04xx On-Chip ECC Yes No Soft Error Rate <0.1 FIT/Mb >150 FIT/Mb <6.25 FIT/Mb Voltage Range V V V Access Time (Max.) 45 ns 35 ns Standby Current (Max.) 8.7 µA 10 µA 7 µA Data Retention Voltage (Min.) 1.0 V 1.2 V 1.5 V 1 Measured PowerSnooze 7

7 Low-Power SRAM (MoBL® : More Battery Life)
Asynchronous SRAM Portfolio High Density | Wide Voltage Range | Automotive A, E1,2 | On-chip ECC3 Fast SRAM Low-Power SRAM (MoBL® : More Battery Life) PowerSnooze™4 Serial SRAM Non-ECC ECC3 Quad-SPI, ECC3 Other Densities NDA Required Contact Sales 32Mb-128Mb CY6218x 64Mb; 2.5, 3.0 V 55 ns; x8, x16 Ind5 Other Densities NDA Required Contact Sales Other Densities NDA Required Contact Sales For Details NDA Required Contact Sales CY7C107x 32Mb; 3.3 V 12 ns; x8, x16 Ind5 CY6217x 32Mb; 2.5, 3.0, 5.0 V 55 ns; x8, x16 Ind5 CY7C106x 16Mb; 1.8, 3.3 V 10 ns; x8, x16, x32 Ind5 CY7C106x 16Mb; V 10 ns; x8, x16, x32 Ind5, Auto E2 CY6216x 16Mb;1.8, 3.0, 5.0 V 45 ns; x8, x16 Ind5, Auto A1 CY6216x 16Mb; V 45 ns; x8, x16, x32 Ind5, Auto E2 CY7S106x 16Mb; V 10 ns; x8, x16, x32 Ind5, Auto E2 CY7C105x 8Mb; 3.3 V 10 ns; x8, x16 Ind5 CY7C Mb; 3.3 V 10 ns; x24 Ind5 CY6215x 8Mb; 1.8, 3.0, 2.5-5V 45 ns; x8, x16 Ind5, Auto A, E1,2 2Mb-16Mb CY7C104x 4Mb; 3.3, 5.0 V 10 ns; x4, x8, x16 Ind5, Auto A, E1,2, RH6 CY7C Mb; 3.3 V 10 ns; x24 Ind5 CY7C104x 4Mb; V 10 ns; x8, x16 Ind5, Auto E2 CY6214x 4Mb; 1.8, 3.0, 2.5-5V 45 ns; x8, x16 Ind5, Auto A, E1,2 CY6214x 4Mb; V 45 ns; x8, x16 Ind5, Auto E2 CY7S104x 4Mb; V 10 ns; x8, x16 Ind5, Auto E2 CY7C1010/11 2Mb; 3.3 V 10 ns; x8, x16 Ind5, Auto A, E1,2 CY7C1024 3Mb; 3.3 V 10 ns; x24 Ind5 CY6213x 2Mb; 1.8, V 45 ns; x8, x16 Ind5, Auto A, E1,2 CY7C1020 512Kb; 2.6, 3.3, 5.0V 10 ns; x16 Ind5, Auto E2 CY7C1019/21/100x 1Mb; 2.6, 3.3, 5.0 V 10 ns; x4, x8, x16 Ind5, Auto A, E1,2 CY6212x 1Mb; V 45 ns; x8, x16 Ind5, Auto A, E1,2 64Kb-1Mb CY7C185 64Kb; 5.0 V 15 ns; x8 Ind5 CY7C19x/ Kb; 3.3, 5.0 V 10 ns; x4, x8 Ind5, Auto A1 CY Kb; 5.0 V 55 ns, 70 ns; x8 Ind5 CY Kb; 1.8, 3.0, 5.0V 55 ns; x8 Ind5, Auto A, E1,2 1 AEC-Q ºC to +85ºC 2 AEC-Q ºC to +125ºC 3 On-chip Error-Correcting Code 4 Fast SRAM with low-power sleep mode 5 Industrial grade -40ºC to +85ºC 6 Radiation hardened, military grade -55ºC to +125ºC New Production Sampling Development/Concept 10

8 4Mb Fast SRAM Family with ECC
Applications Family Table Switches and routers IP phones Test equipment Automotive Computation servers Military and aerospace systems Density MPN Access Time Supply Current (Max. at 85ºC) 4 Mb CY7C104x 10 ns 45 mA 16 CY7C106x 110 Features Block Diagram Access time: 10 ns for 4Mb (see Family Table) Bus-width configurations: x8, x16 for 4Mb Wide operating voltage range: V Error-Correcting Code (ECC) to detect/correct single-bit errors Bit-interleaving to avoid multi-bit errors Error-indication (ERR) pin to indicate single-bit errors Industrial and automotive grades Industry-standard, RoHS-compliant packages Fast SRAM with ECC SRAM Array Address Decoder ECC Encoder Input Buffer 8, 16 18-23 Data I/O Mux ERR Address SRAM Array Sense Amps ECC Decoder Control Logic CE OE WE BHE1 BLE2 Collateral Availability Preliminary Datasheet: Contact Sales Sampling: Now Production: Q3 2015 1 Byte high enable 2 Byte low enable 11a

9 4Mb MoBL® SRAM Family With ECC
Applications Family Table Programmable logic controllers Handheld devices Multifunction printers Automotive Implantable medical devices Computation servers Density MPN Standby Current (Max. at 85ºC) Standby Current (Typ. at 25ºC) 4 Mb CY6214x 8.7 µA 3.7 16 CY6216x 5.3 Features Block Diagram Access time: 45 ns for 4Mb Standby Current: 8.7 µA for 4Mb Bus-width configurations: x8, x16 for 4Mb Wide operating voltage range: V Error-Correcting Code (ECC) to detect/correct single-bit errors Bit-interleaving to avoid multi-bit errors Error-indication (ERR) pin to indicate single-bit errors Industrial and automotive grades Industry-standard, RoHS-compliant packages MoBL®3 SRAM with ECC CE OE WE BHE1 BLE2 I/O Mux Address Decoder Sense Amps ECC Decoder Input Buffer ECC Encoder Control Logic SRAM Array 18-23 Address Data 8, 16 ERR Collateral Availability Preliminary Datasheet: Contact Sales Sampling: Now Production: Q3 2015 1 Byte high enable 2 Byte low enable 3 More Battery Life 11b

10 4Mb Fast SRAM Family with PowerSnooze™
Applications Family Table Programmable logic controllers Handheld devices Multifunction printers Automotive Computation servers Density MPN Access Time Deep Sleep Current (Max. at 85ºC) 4 Mb CY7S104x 10 ns 15 µA 16 CY7S106x 22 Features Block Diagram Access time: 10 ns for 4Mb (see Family Table) PowerSnooze: Additional power-saving (deep-sleep) mode Deep-sleep current: 15 µA for 4Mb (see Family Table) Bus-width configurations: x8, x16 for 4Mb Wide operating voltage range: V Error-Correcting Code (ECC) to detect/correct single-bit errors Bit-interleaving to avoid multi-bit errors Industrial and automotive grades Industry-standard, RoHS-compliant packages Fast SRAM with PowerSnooze™ ECC Encoder Input Buffer Address Decoder 8, 16 20 SRAM Array I/O Mux Data Address ERR Power Management Block (Enables PowerSnooze) Sense Amps ECC Decoder Control Logic DS1 CE OE WE BHE2 BLE3 Collateral Availability Preliminary Datasheet: Contact Sales Sampling: Now Production: Q3 2015 1 Deep-sleep 2 Byte high enable 3 Byte low enable 11c

11 Here’s How To Get Started
Visit the Asynchronous SRAM with ECC webpage: Download the roadmap for Asynchronous SRAMs: Request a preliminary datasheet: Contact Sales 12

12 APPENDIX 15

13 Product Selector Guide: 4Mb MoBL SRAM
Part Number Bus Width Access Time # CE Pins ERR Pin Voltage Temp Package CY62147G30-45BVXI x16 45 ns 1 No V -40-85°C 48-VFBGA CY62147G30-45ZSXI 44-TSOP II CY62148G30-45ZSXI x8 CY62147GE30-45BVXI Yes CY62147GE30-45ZSXI CY62147G18-55BVXI 55 ns V CY62146G30-45ZSXI CY62148G30-45SXI 32-SOIC CY62146GE30-45ZSXI CY621472G30-45ZSXI 2 CY62148G-45ZSXI V 32-TSOP II CY62147G30-45B2XI 4Mb MoBL SRAM Part Numbering Decoder CY X GX XX - XX XX X XI Pb-free Industrial Temperature Grade Chip Enable: Blank = Dual-Chip Enable, 1 = Single-Chip Enable Package Type: BV = 48-VFBGA, ZS = 44-TSOP II, S = 32-SOIC Speed Grade: 45 = 45 ns, 55 = 55 ns Voltage Range: 30 = V, 18 = V, Blank = V Process Technology: G = 65nm; X: E = ERR Pin, Blank = No ERR Pin Bus Width: 7 = x16, 8 = x8 6214: 4Mb MoBL SRAM Family Company ID: CY = Cypress 16a

14 Product Selector Guide: 4Mb Fast SRAM
Part Number Bus Width Access Time # CE Pins ERR Pin Voltage Temp Package CY7C1049G30-10ZSXI x8 10 ns 1 No V -40-85°C 44-TSOP II CY7C1049GE30-10VXI Yes 36-SOJ CY7C1041G30-10ZSXI x16 CY7C1041GE30-10ZSXI CY7C1049G-10VXI V CY7C1041G-10ZSXI CY7C1041G30-10BVXI 48-VFBGA CY7C1041G-10VXI 44-SOJ CY7C1041G18-15BVXI 15 ns V CY7C1041G30-10BVJXI CY7C1041G30-10VXI CY7C1049G-10ZSXI 16Mb Fast SRAM Part Numbering Decoder CY 7C104 X GX XX - XX XXX XI Pb-free Industrial Temperature Grade Package Type: ZS = 44-TSOP II, V = 36-SOJ, BVX = 48-VFBGA Speed: 10 = 10 ns, 15 = 15 ns Voltage Range: 18 = V, 30 = V, Blank= V Process Technology: G = 65nm; X: E = ERR Pin, Blank = No ERR Pin Bus Width: 1 = x16, 9 = x8 7C104: 4Mb Fast SRAM Family Company ID: CY = Cypress 16b

15 Product Selector Guide: 4Mb PowerSnooze SRAM
Part Number Bus Width Access Time # CE Pins ERR Pin Voltage Temp Package CY7S1041G30-10BVXI x16 10 ns 1 No V -40-85°C 48-VFBGA CY7S1049G30-10VXI x8 36-SOJ CY7S1041G30-10ZSXI 2 44-TSOP II 16Mb PowerSnooze SRAM Part Numbering Decoder CY 7S104 X GX XX - XX XXX I Temperature Grade: Industrial Pb-free Package Type: VX = 36-pin SOJ, ZSX = 44-pin TSOP II, BVX = 48-ball VFBGA Speed: 10 = 10 ns Voltage Range: 30 = V Process Technology: G = 65nm; X: E = ERR Pin, Blank = No ERR Pin Bus Width: 1 = x16, 9 = x8 7S104: 4Mb PowerSnooze family (deep-sleep feature) Company ID: CY = Cypress 16c

16 References and Links Asynchronous SRAM with ECC webpage: Getting Started with Asynchronous SRAM webpage: Asynchronous SRAM roadmap: Cypress Product Selector Guide: Knowledge Base articles: Asynchronous SRAM datasheets: Asynchronous SRAM App Notes: SRAM Board Design Guidelines: 4Mb Asynchronous SRAM with ECC preliminary datasheets: Contact Sales 18

17 4Mb MoBL ECC SRAM Solution Value
$4.11 $1.64 $0.01 $0.15 $0.16 $5.91 Competitor Asynchronous Low-power SRAM (IS62WV25616DBLL-45TLI) without ECC Price $4.111 BOM Integration Additional SRAM for ECC data (IS62WV6416DBLL-45TLI) Price $1.642 Additional Value Board Space Savings ECC Value Added $0.013 Cost of Programming MCU for ECC logic Value Added $0.154 Competitor IS62WV6416DBLL-45TLI BOM Integration Value Board Space Savings Cost of Programming MCU for ECC Logic Total Additional Value Total Value Delivered Async MPWR SRAM with ECC: Total Cost: 25% Total Savings: CY62146G30-45ZXSI $4.461 $1.45 4 5 man-weeks at $3,000 per man-week = $15,000 (amortized over 100ku) 19a

18 4Mb Fast ECC SRAM with PowerSnooze
$3.52 $1.96 $5.48 Competitor Asynchronous Fast SRAM (IS61WV25616EDBLL-10TLI) without ECC Price $3.521 Additional Value PowerSnooze: Reduction in battery cost based on power savings. Assuming the application is battery backed, is in standby 20% of operating time and runs 12 hours a day for six years Competitor PowerSnooze Total Additional Value Total Value Delivered Async Fast SRAM with ECC and PowerSnooze: Total Cost: 12% Total Savings: CY7S1041G30-10ZSXI $4.823 $0.66 Additional value calculation: Total device standby time 6 × 12 × 365 × 20% = 5256 hours IS61WV25616EDBLL-10TLI power consumption in standby mode 3.3 V × 6 mA = 19,800 µW CY Fast with PowerSnooze power consumption in standby mode 3.3 V × 15 µA = 49.5 µW Thus, power savings 19,800 µW – 49.5 µW = 19,750 µW = kW Battery cost savings per hour $18.90/kWh2 × kW = $ Total savings for 5,256 hours (Total value delivered) 5,256 × $ = $1.96 2 Battery cost per kWh = $18.90 3 Projected Digikey 1ku price 19b

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