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Reactive Clocks with Variability-Tracking Jitter

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Presentation on theme: "Reactive Clocks with Variability-Tracking Jitter"— Presentation transcript:

1 Reactive Clocks with Variability-Tracking Jitter
Jordi Cortadella, Luciano Lavagno, Pedro López, Marc Lupon, Alberto Moreno, Antoni Roca and Sachin S. Sapatnekar Universitat Politècnica de Catalunya Politecnico di Torino University of Minnesota

2 The cost of variability
margins frequency Reactive Clocks ICCD 2015

3 The cost of variability
Goal: Reduce margins Impact: Speed Energy margins frequency Reactive Clocks ICCD 2015

4 Timing Combinational Logic PLL Flip Flops Flip Flops Reactive Clocks
ICCD 2015

5 Timing: setup constraint
Comb. Logic PVTA variability Two competing paths: Launching path Capturing path Launching path < Capturing path + Period No variability (or very little) PLL 1 2 1 1 2 2 + Margins Reactive Clocks ICCD 2015

6 Outline Reactive Clocks: how they work Understanding variability:
Global/Local, Static/Dynamic Quantifying the benefits of Reactive Clocks Conclusions Reactive Clocks ICCD 2015

7 Correlated! Reactive Clock PVTA variability + Margins Comb. Logic
Launching path < Capturing path + Period PLL + Margins Reactive Clocks ICCD 2015

8 Variability: PLL vs. Reactive Clock
Q D time launching path capturing path PLL period Reactive Clocks ICCD 2015

9 Variability: PLL vs. Reactive Clock
Q D PLL period time launching path capturing path Q D clock-data compensation PLL period margin Q D Reactive Clock Reactive Clocks ICCD 2015

10 PLL vs. Reactive Clock Adaptive frequency Fixed frequency
Reactive Clk (1.2V) Adaptive frequency 30% PLL (1.2V) Fixed frequency Reactive Clk (0.85V) Vdd = 1.2V  30% Reactive Clocks ICCD 2015

11 Outline Reactive Clocks: how they work Understanding variability:
Global/Local, Static/Dynamic Quantifying the benefits of Reactive Clocks Conclusions Reactive Clocks ICCD 2015

12 Understanding variability
WID (local) D2D (global) Source: H. Masuda et al. (ICICC 2005) Reactive Clocks ICCD 2015

13 Understanding variability
Static Dynamic Slow (ms) Dynamic Fast (ns) Global (corners) PV VTA V Local (OCV) Margins Worst-case sign-off Binning Static Variability (PV) Dynamic Variability (VTA) Static Variability (PV) Global X Local Reactive Clocks Static Variability (PV) Dynamic Variability (VTA) X Margins removed after binning Only margins for local dynamic variability Reactive Clocks ICCD 2015

14 Outline Reactive Clocks: how they work Understanding variability:
Global/Local, Static/Dynamic Quantifying the benefits of Reactive Clocks Conclusions Reactive Clocks ICCD 2015

15 Reactive Clock Gain: 40% less Energy or 1.6x speed-up Pain: Negligible
Clock domain Risk: Zero Enable Original circuit not modified Negligible area Post-tapeout calibration (by SW) Conventional timing (PrimeTime) PLL Reactive Clock Reactive Clocks ICCD 2015

16 PLL vs. Reactive Clocks DUT SPICE models (65nm) temperature 25oC 125oC
Rclk Reactive Clocks ICCD 2015

17 PLL vs. Reactive Clocks DUT SPICE models (65nm) temperature 25oC 125oC
Rclk Slow 125oC Timing sign-off Reactive Clocks ICCD 2015

18 PLL vs. Reactive Clocks DUT SPICE models (65nm) temperature 25oC 125oC
Rclk Typical 125oC Slow 125oC Timing sign-off Ideal binning Reactive Clocks ICCD 2015

19 PLL vs. Reactive Clocks DUT SPICE models (65nm) temperature 25oC 125oC
Rclk Typical 125oC Slow 75oC Slow 125oC Timing sign-off Reactive Clocks ICCD 2015

20 PLL vs. Reactive Clocks DUT SPICE models (65nm) temperature 25oC 125oC
Rclk Rclk Typical 125oC Slow 75oC Typical 75oC Slow 125oC Timing sign-off Reactive Clocks ICCD 2015

21 and great benefits for hostile environmental conditions (> 2x)
PLL vs. Reactive Clocks DUT SPICE models (65nm) temperature 25oC 125oC 75oC PLL PLL Rclk Rclk and great benefits for hostile environmental conditions (> 2x) Typical 125oC Slow 75oC Typical 75oC Slow 125oC 1.2x Timing sign-off 1.6x Reactive Clocks ICCD 2015

22 Energy reduction (@iso-performance)
PLL vs. Reactive Clocks DUT SPICE models (65nm) temperature 25oC 125oC 75oC PLL PLL Rclk Rclk sign-off -42% (0.91V) -20% (1.07V) slow die typical die Energy reduction Reactive Clocks ICCD 2015

23 Synthesis of the Ring oscillator
Delay PLL period OCV Critical paths Library Corners Programmable by SW Reactive Clocks ICCD 2015

24 Conclusions Moore’s law is (economically) over. It’s time to exploit what is left in established nodes. What’s left? Margins for dynamic variability. Reactive Clocks: a zero-risk technology to boost performance (1.6x speedup) or reduce energy (40%) Thank you! Reactive Clocks ICCD 2015

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