1. Instructor: Tor Aamodt
EECE 259: Introduction to Microcomputers Slide Set 7: The Von Neumann Architecture. 2’s Complement; Binary Arithmetic using Combinational Logic 1
Instructor: Tor Aamodt

2. Learning Objectives
By the end of this slide set you should be able to:
Differentiate between a high level language (C, Java), assembly code and machine code.
List, in order, the basic instruction processing steps found inside all Von Neumann style computers
Perform addition and subtraction using the 2’s complement binary representation
Explain how a ripple carry adder works
Design a addition/subtraction unit
Design a binary multiplier
Design simple arithmetic circuits in VHDL

3. The Instruction Set: a Critical Interface
software
instruction set
hardware
Analogy: Instructions = steps in a cookbook recipe

4. Instruction Set Architecture (ISA)
Important acronym: ISA
Instruction Set Architecture
The low-level software interface to the machine
Language of the machine
Must translate any programming language into this language
Examples: x86_64 (64-bit x86 Intel instruction set), MIPS, SPARC, Alpha, PA-RISC, PowerPC, ARM
ISA is the set of features “visible to programmer”
instruction set
software
hardware

5. Levels of Representation
temp = v[k];
v[k] = v[k+1];
v[k+1] = temp;
High Level Language Program
“semantic gap”
1960s-70s CISC
tries to “narrow” gap by bringing hardware “up”
closer to programming languages such as C/Prolog/Lisp
Compiler
Assembly Language Program
LDR R5, [R2]
LDR R6, [R2, #4]
STR R6, [R2]
STR R5, [R2, #4]
Assembler
Machine Language Program
Machine Interpretation
Control Signal Specification
ALUOP[0:3] ← InstrReg[9:12] & MASK

6. Fundamental Execution Cycle
Does “instruction fetch” of next instruction depend upon result of last instruction? (Pick “best” answer.)
A: Yes
B: No
C: Maybe ?
D: Not sure
Does “instruction fetch” of next instruction depend upon result of last instruction? (Pick “best” answer.)
A: Yes
B: No
C: Maybe
D: Not sure
Memory
Instruction
Fetch
Decode
Operand
Execute
Result
Store
Next
Obtain instruction from program storage
Processor
program
Determine required actions and instruction size
regs
F.U.s
Data
Locate and obtain operand data
Compute result value or status
von Neuman Architecture
(stored program computer)
Deposit results in storage for later use
Determine successor instruction

7. Numbers Digital logic works with binary numbers
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Numbers
Digital logic works with binary numbers
Each bit has a value based on its position
e.g., 10101
= 21
Or = -11

8. From Decimal To Binary Example: 1910 Convert number to binary base:
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From Decimal To Binary
Example: 1910
Convert number to binary base:
19 ÷ 2 = 9 remainder 1
9 ÷ 2 = 4 remainder 1
4 ÷ 2 = 2 remainder 0
2 ÷ 2 = 1 remainder 0
1 ÷ 2 = 0 remainder 1
1910 =
LSB
MSB

9. 1/18/2005
From Decimal To Binary
Iteratively subtract largest power of 2 smaller than number:
Example: 1910
Convert number to binary base, using subtraction
= 3
= 1
= 0
1910 = = =

10. Hexadecimal numbers
Hexadecimal, ‘hex’, or base-16, number system is very convenient when working with computers.
Mainly, it is shorter and faster to write than binary.
It is far easier to convert between binary and ‘hex’ than between binary and decimal.
Four bits can represent 24 = 16 different things.
We take four bits, give them the 16 labels 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, A, B, C, D, E, F

11. Hexadecimal numbers Binary Decimal Hexadecimal 0000 0001 1 0010 2 0011
0001 1
0010 2
0011 3
0100 4
0101 5
0110 6
0111 7
1000 8
1001 9
1010 10 A
1011 11 B
1100 12 C
1101 13 D
1110 14 E
1111 15 F

12. From Decimal To Binary To Hexadecimal
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From Decimal To Binary To Hexadecimal
Example: =
What is 0111 in HEX?
A: A
B: B
C: 7
D: D
E: Not sure
What is 0111 in HEX?
A: A
B: B
C: 7 ✔
D: D
E: Not sure 7
Ahex
Bhex
What is 1010 in HEX?
A: A
B: B
C: 7
D: D
E: Not sure
What is 1010 in HEX?
A: A ✔ (8+2=10=>A)
B: B
C: 7
D: D
E: Not sure
=939
=427
=171
=43
43-32=11
11-8=3
3-2=1
1-1=0
What is 1010 in HEX?
A: A
B: B
C: 7
D: D
E: Not sure
What is 1010 in HEX?
A: A
B: B ✔ (8+2+1=11=>B)
C: 7
D: D
E: Not sure

13. Binary addition 1-bit 0+0 = 0, 1+0 = 1, 1+1 = 10 110_ 0_ 10_ 1_ 11_
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Binary addition
1-bit 0+0 = 0, 1+0 = 1, 1+1 = 10
110_ 0_
10_ 1_
11_
111_ 9
1001 01
001 1 12
1100
100 00

14. One bit of an adder Counts the number of “1” bits on its input
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Counts the number of “1” bits on its input
Outputs the result in binary
For a half-adder, 2 inputs, output can be 0, 1, or 2
For a full-adder, 3 inputs, output can be 0, 1, 2, or 3

15. Half Adder What Boolean function of a and b gives s? A: AND B: OR
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Half Adder
ab cs
# 00 00
# 01 01
# 10 01
# 11 10
-- half adder
library ieee;
use ieee.std_logic_1164.all;
entity HalfAdder is
port( a, b: in std_logic;
c, s: out std_logic );
end HalfAdder;
architecture impl of HalfAdder is
begin
s <= a xor b;
c <= a and b;
end impl;
What Boolean function of a and b gives s?
A: AND
B: OR
C: XOR
D: XNOR
E: Not sure
What Boolean function of a and b gives c?
A: AND ✔
B: OR
C: XOR
D: XNOR
E: Not sure
What Boolean function of a and b gives c?
A: AND
B: OR
C: XOR
D: XNOR
E: Not sure
What Boolean function of a and b gives s?
A: AND
B: OR
C: XOR ✔
D: XNOR
E: Not sure

16. Full Adder Counts the number of “1” bits on its input
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Full Adder
Can “c” output of rightmost HA ever be ‘1’ (for any combination of a, b and c input values)?
A: Yes
B: No
C: Not sure
Can “c” output of rightmost HA ever be ‘1’ (for any combination of a, b and c input values)?
A: Yes
B: No ✔
C: Not sure
Counts the number of “1” bits on its input
For a full-adder, 3 inputs, output can be 0, 1, 2, or 3
Can build from multiple half adders…

17. -- full adder - from half adders library ieee;
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-- full adder - from half adders
library ieee;
use ieee.std_logic_1164.all;
use work.ch10.all;
entity FullAdder is
port( a, b, cin: in std_logic;
cout, s: out std_logic );
end FullAdder;
architecture impl of FullAdder is
signal g, p: std_logic; -- generate and propagate
signal cp: std_logic;
begin
HA1: HalfAdder port map(a,b,g,p);
HA2: HalfAdder port map(cin,p,cp,s);
cout <= g or cp;
end impl;
Includes package containing component declaration for HalfAdder.

18. Full adder from a truth table
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Full adder from a truth table

19. Full adder from truth table
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Full adder from truth table
-- full adder - logical
architecture logical_impl of FullAdder is
begin
s <= a xor b xor cin;
cout <= (a and b) or (a and cin) or (b and cin);
end logical_impl;

21. CMOS Version of Full Adder
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CMOS Version of Full Adder

22. 1/18/2005
Multi-bit Adder

23. Adder in VHDL - behavioral
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Adder in VHDL - behavioral
-- multi-bit adder - behavioral
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity Adder is
generic( n: integer := 8 );
port( a, b : in std_logic_vector(n-1 downto 0);
cin: in std_logic;
cout: out std_logic;
s: out std_logic_vector(n-1 downto 0));
end Adder;
architecture impl of Adder is
signal sum: std_logic_vector(n downto 0);
begin
sum <= ('0' & a) + ('0' & b) + cin;
cout <= sum(n);
s <= sum(n-1 downto 0);
end impl;

25. Ripple-carry adder – bit-slice notation
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Ripple-carry adder – bit-slice notation
-- multi-bit adder - bit-by-bit logical
architecture ripple_carry_impl of Adder is
signal p, g: std_logic_vector(n-1 downto 0);
signal c: std_logic_vector(n downto 0);
begin
p <= a xor b; -- propagate
g <= a and b; -- generate
c <= (g or (p and c(n-1 downto 0))) & cin; -- carry = g or (p and c)
s <= p xor c(n-1 downto 0); -- sum
cout <= c(n);
end ripple_carry_impl;

26. 1/18/2005
Negative Integers
Thus far we have only addressed positive integers. What about negative numbers?
3 ways to represent negative integers in binary:
Sign Magnitude
One’s complement
Two’s complement
Example: Consider –23
Sign Magnitude
One’s complement
Two’s complement

27. Converting Positive to Negative
To convert a positive number in 2’s complement to a negative number:
invert bits and then add 1
E.g., convert 0011 to negative number:
step 1: (flip all bits)
step 2: (add one)
1101 (-3 in 2’s complement)

28. Converting Negative to Positive
-7 as a 4-bit number in 2’s complement equals:
A: 1101
B: 1000
C: 1001 ✔ (7=0111; =1001)
D: 1011
E: Not sure
-5 as a 4-bit number in 2’s complement equals:
A: 0101
B: 1101
C: 1010
D: ✔ ( )
E: Not sure
-5 as a 4-bit number in 2’s complement equals:
A: 0101
B: 1101
C: 1010
D: 1011
E: Not sure
-1 as a 4-bit number in 2’s complement equals:
A: 1111
B: 1101
C: 1011
D: 1001
E: Not sure
-1 as a 4-bit number in 2’s complement equals:
A: 1111 ✔ (1=0001; =1111)
B: 1101
C: 1011
D: 1001
E: Not sure
-7 as a 4-bit number in 2’s complement equals:
A: 1101
B: 1000
C: 1001
D: 1011
E: Not sure
Converting Negative to Positive
Use same operation to convert back
E.g., convert 1101 (-3) to positive number:
step 1: (flip all bits)
step 2: (add one)
0011 (3 in 2’s complement)

29. Why do we all use 2’s complement?
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Why do we all use 2’s complement?
2’s complement makes subtraction easy
Represent negative number, –x as 2n – x
All arithmetic is done modulo 2n so no adjustments are necessary
x + (– y) = x + (2n – y) (mod 2n)
consider 4-bit numbers
4 – 3 = 4 + (16 – 3) (mod 16) = 4 + (15 – 3 + 1) = (1111 – 0011) = = 0001

30. 1/18/2005
2’s Complement

31. 1/18/2005

32. 1/18/2005

33. Overflow If using 4-bits, 4 + 4 = 8 which cannot fit into 4-bit
If using 4-bits, -6 + (-3) = -9 which cannot fit inside 4-bits

34. Detecting Overflow

35. Alternative implementationas bs
cis qs
cos
ovf
comment
Both inputs positive, both carries 0, no overflow 1
Both inputs positive, carry in 1, overflow
Inputs signs different, carry in 0, no overflow
Inputs signs different, carry in 1, no overflow
Both inputs negative, carry in 0, overflow
Both inputs negative, carry in 1, no overflow

36. 1/18/2005

37. -- add a+b or subtract a-b, check for overflow library ieee;
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-- add a+b or subtract a-b, check for overflow
library ieee;
use ieee.std_logic_1164.all;
use work.ch10.all;
entity AddSub is
generic( n: integer := 8 );
port( a, b: in std_logic_vector(n-1 downto 0);
sub: in std_logic; -- subtract if sub=1, otherwise add
s: out std_logic_vector(n-1 downto 0);
ovf: out std_logic ); -- 1 if overflow
end AddSub;
architecture impl of AddSub is
signal c1, c2: std_logic; -- carry out of last two bits
begin
ovf <= c1 xor c2; -- overflow if signs don't match
-- add non sign bits
Ai: Adder generic map(n-1)
port map( a(n-2 downto 0), b(n-2 downto 0) xor (n-2 downto 0 => sub),
sub, c1, s(n-2 downto 0) );
-- add sign bits
As: Adder generic map(1)
port map( a(n-1 downto n-1), b(n-1 downto n-1) xor (0 downto 0 => sub),
c1, c2, s(n-1 downto n-1) );
end impl;

38. Compare two numbers with subtraction
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Compare two numbers with subtraction
diff = a – b if diff is negative (sign bit = 1), a<b
If diff is zero, a=b
Example, compare a = 0101 and b = 0110
diff = a – b = 1111 => a<b
Compare a=0111 and b = 0111, diff = 0 => a=b

39. Multiplication Multiplication Shifting left multiplies by 2
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Multiplication
Multiplication
Shifting left multiplies by 2
e.g., 5 = 101, 10 = 1010, 20 = 10100
To multiply by 3, compute 3x = x + 2x
Example, 7 x 5 x

40. First generate partial products: pij = ai  bj has weight i+j
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First generate partial products: pij = ai  bj has weight i+j

41. Then sum partial products to get sum
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Then sum partial products to get sum

42. use ieee.std_logic_1164.all; use work.ch10.all; entity Mul4 is
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library ieee;
use ieee.std_logic_1164.all;
use work.ch10.all;
entity Mul4 is
port( a, b: in std_logic_vector(3 downto 0);
p: out std_logic_vector(7 downto 0) );
end Mul4;
architecture impl of Mul4 is
signal pp0, pp1, pp2, pp3, s1, s2, s3: std_logic_vector(3 downto 0);
signal cout1, cout2, cout3: std_logic;
begin
-- form partial products
pp0 <= a and (3 downto 0=>b(0));
pp1 <= a and (3 downto 0=>b(1));
pp2 <= a and (3 downto 0=>b(2));
pp3 <= a and (3 downto 0=>b(3));
-- sum up partial products
A1: Adder generic map(4) port map(pp1, '0' & pp0(3 downto 1),'0',cout1,s1);
A2: Adder generic map(4) port map(pp2,cout1 & s1(3 downto 1),'0',cout2,s2);
A3: Adder generic map(4) port map(pp3,cout2 & s2(3 downto 1),'0',cout3,s3);
-- collect the result
p <= cout3 & s3 & s2(0) & s1(0) & pp0(0);
end impl;

43. use ieee.std_logic_1164.all; use ieee.std_logic_unsigned.all;
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library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.std_logic_arith.all;
entity testbench_Mul4 is
end testbench_Mul4;
architecture test of testbench_Mul4 is
signal a, b : std_logic_vector(3 downto 0);
signal output : std_logic_vector(7 downto 0);
signal err : std_logic;
signal prod : std_logic_vector(7 downto 0);
begin
DUT: entity work.Mul4(impl) port map(a,b,output);
process
err <= '0';
for i in 0 to 15 loop
a <= conv_std_logic_vector(i,4);
for j in 0 to 15 loop
b <= conv_std_logic_vector(j,4);
wait for 10 ns;
prod <= a * b;
report to_string(a) & " * " & to_string(b) & " = " & to_string(output);
if not (prod = output) then
err <= '1';
end if;
end loop;
if err = '0' then report "PASSED"; else report "FAILED"; end if;
wait;
end process;
end test;

44. 1/18/2005
# 0 * 0 = 0
# 1 * 0 = 0
# 1 * 1 = 1
# 2 * 0 = 0
# 2 * 1 = 2
# 2 * 2 = 4
# 3 * 0 = 0
# 3 * 1 = 3
# 3 * 2 = 6
# 3 * 3 = 9
# 4 * 0 = 0
# 4 * 1 = 4
# 4 * 2 = 8
# 4 * 3 = 12
# 4 * 4 = 16
# 5 * 0 = 0
# 5 * 1 = 5
# 5 * 2 = 10
# 5 * 3 = 15
# 5 * 4 = 20
# 5 * 5 = 25
# 6 * 0 = 0
# 6 * 1 = 6
# 6 * 2 = 12
# 6 * 3 = 18
# 6 * 4 = 24
# 6 * 5 = 30
# 6 * 6 = 36
# 7 * 0 = 0
# 7 * 1 = 7
# 7 * 2 = 14
# 7 * 3 = 21
# 7 * 4 = 28
# 7 * 5 = 35
# 7 * 6 = 42
# 7 * 7 = 49
# 8 * 0 = 0
# 8 * 1 = 8
# 8 * 2 = 16
# 8 * 3 = 24
# 8 * 4 = 32
# 8 * 5 = 40
# 8 * 6 = 48
# 8 * 7 = 56
# 8 * 8 = 64
# 9 * 0 = 0
# 9 * 1 = 9
# 9 * 2 = 18
# 9 * 3 = 27
# 9 * 4 = 36
# 9 * 5 = 45
# 9 * 6 = 54
# 9 * 7 = 63
# 9 * 8 = 72
# 9 * 9 = 81
# 10 * 0 = 0
# 10 * 1 = 10
# 10 * 2 = 20
# 10 * 3 = 30
# 10 * 4 = 40
# 10 * 5 = 50
# 10 * 6 = 60
# 10 * 7 = 70
# 10 * 8 = 80
# 10 * 9 = 90
# 10 * 10 = 100
# 11 * 0 = 0
# 11 * 1 = 11
# 11 * 2 = 22
# 11 * 3 = 33
# 11 * 4 = 44
# 11 * 5 = 55
# 11 * 6 = 66
# 11 * 7 = 77
# 11 * 8 = 88
# 11 * 9 = 99
# 11 * 10 = 110
# 11 * 11 = 121
# 12 * 0 = 0
# 12 * 1 = 12
# 12 * 2 = 24
# 12 * 3 = 36
# 12 * 4 = 48
# 12 * 5 = 60
# 12 * 6 = 72
# 12 * 7 = 84
# 12 * 8 = 96
# 12 * 9 = 108
# 12 * 10 = 120
# 12 * 11 = 132
# 12 * 12 = 144
# 13 * 0 = 0
# 13 * 1 = 13
# 13 * 2 = 26
# 13 * 3 = 39
# 13 * 4 = 52
# 13 * 5 = 65
# 13 * 6 = 78
# 13 * 7 = 91
# 13 * 8 = 104
# 13 * 9 = 117
# 13 * 10 = 130
# 13 * 11 = 143
# 13 * 12 = 156
# 13 * 13 = 169
# 14 * 0 = 0
# 14 * 1 = 14
# 14 * 2 = 28
# 14 * 3 = 42
# 14 * 4 = 56
# 14 * 5 = 70
# 14 * 6 = 84
# 14 * 7 = 98
# 14 * 8 = 112
# 14 * 9 = 126
# 14 * 10 = 140
# 14 * 11 = 154
# 14 * 12 = 168
# 14 * 13 = 182
# 14 * 14 = 196
# 15 * 0 = 0
# 15 * 1 = 15
# 15 * 2 = 30
# 15 * 3 = 45
# 15 * 4 = 60
# 15 * 5 = 75
# 15 * 6 = 90
# 15 * 7 = 105
# 15 * 8 = 120
# 15 * 9 = 135
# 15 * 10 = 150
# 15 * 11 = 165
# 15 * 12 = 180
# 15 * 13 = 195
# 15 * 14 = 210
# 15 * 15 = 225

45. Summary Binary number representation Add numbers a bit at a time
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Summary
Binary number representation
Add numbers a bit at a time
2’s complement –x = (2n – x) = (2n – 1) – x + 1 = neg(x) + 1
Subtract by 2’s complement and add
Multiply – form partial products pij and sum
Number representation – accuracy and resolution.
Fixed and floating point

46. Lab 6 Adding FSM Controller to Datapath
Possibly most important lab in term (key to connecting digital hardware with computer programming)

47. Datapath Additions PC = Program Counter (address of next instruction)
IR = Instruction Register (16-bits that tell computer what to do next)

48. Datapath Changes (1)

49. Datapath Changes (2)

50. Datapath Controller (FSM)

51. Instruction Decoder

52. Instructions
Suggestion: implement “ALU Instructions” first

53. Example State Machine

54. Announcements Oct 15
Midterm: See room assignment in grade book on connect
Lab 6 next week (worth 6.67%)
Code for Lab 5 datapath posted (use in case you did not finish Lab 5 and you don’t know anyone else who did either)

55. Announcements Oct 17 Lab 6 next week (worth 6.67%)
Code for Lab 5 datapath posted (use in case you did not finish Lab 5 and you don’t know anyone else who did either)