1. Some VHDL Details
10/8/08
ECE Lecture 8

2. Lecture Overview Language Elements Examples of VHDL of FSMs The Entity
The Architecture
Types needed for FSM modeling
Signal Declaration
Sequential Statements – what goes inside process
Examples of VHDL of FSMs
10/8/08
ECE Lecture 8

3. The Entity Will only use formal_port_clause
entity_declaration::=
entity identifier is
entity_header
entity_declarative_part
[begin
entity_statement_part]
end [identifier];
entity_header::= [formal_generic_clause]
[formal_port_clause]
Will only use formal_port_clause
Will not use entity_declarative_part
Will never have entity_statement_parts
10/8/08
ECE Lecture 8

4. The Entity ENTITY your_descriptor IS PORT(x,y,z : IN BIT;
o1,o2,o3 : OUT BIT;
clk : IN BIT);
END your_descriptor;
Only need to have inputs, outputs, and the clock in the Entity when doing a FSM.
10/8/08
ECE Lecture 8

5. Signal types
The input and output signals will typically be of the following types for FSM modeling
BIT, or BIT_VECTOR
STD_LOGIC or STD_LOGIC_VECTOR
BIT and BIT_VECTOR signals have a value of ‘0’ or ‘1’
STDSTD_LOGIC or STD_LOGIC_VECTOR signals have a value of ‘U’, ‘L’, ‘0’, ‘W’, ‘X’, ‘H’, ‘1’, ‘Z’, ‘-’
10/8/08
ECE Lecture 8

6. The Architecture The declarative part first
architecture identifier of entity_name is
architecture_declarative_part
begin
architecture_statement_part
end [identifier];
The declarative part first
architecture_declarative_part::=
{architecture_declarative_item}
10/8/08
ECE Lecture 8

7. Architectural Declarative Items
For FSM modeling will have two typical lines
An Enumeration Type for specifying the states
TYPE state_type IS (ST_1, ST_2, …., ST-n);
A declaration of a signal of that type for the current and next state
SIGNAL state, next_state : state_type;
These could be initialized if desired.
10/8/08
ECE Lecture 8

8. Initialization when declard
To initialize the initial value of state and next_state at declaration
SIGNAL state,next_state: state_type :=ST_0;
By default the initial value of an enumeration type is the leftmost value of the set of value for the type. So here it would be ST_0
10/8/08
ECE Lecture 8

9. So Far ARCHITECTURE one OF your_descriptor IS BEGIN
TYPE state_type IS (INIT,L1,L2,L3,R1,R2,R3,LR3);
SIGNAL state, next_state : state_type := INIT;
BEGIN
You may have a few other signals to connect up some internal signals.
These are like wires on a circuit board.
10/8/08
ECE Lecture 8

10. The Process The VHDL PROCESS statement
This is a sequential statement of the language
The code within the process is executed sequentially – similar to C, C++, C#
Each process is independent on the other processes and each executes concurrently
10/8/08
ECE Lecture 8

11. The PROCESS Statement The process label is optional.
process [ (sensitivity_list) ]
process_declarative_part
begin
process_statement_part -- {sequential statement}
end process [process_label];
The process label is optional.
The sensitivity list is very important for FSM modeling
You will typically not have any declarations to make that have scope just over this process
The process_statement_part is any sequential language structure
10/8/08
ECE Lecture 8

12. The sequential statements
Sequential Statements are like the statements of any procedural programming language.
They are executed sequentially according to the control flow of the code.
Time introduced using special language statements. Only in the F/F process.
10/8/08
ECE Lecture 8

13. The F/F process
Have seen a process for a simple D F/F with no preset or clear
PROCESS
BEGIN
WAIT UNTIL clk=‘1’ and clk’event;
state <= next_state;
END PROCESS;
This process is very good provided all you need is a F/F and no preset or clear
But what if you need them? As is often the case.
10/8/08
ECE Lecture 8

14. A more robust D F/F A D F/F with preset and clear
Both preset and clear are active low
PROCESS (clk,preset,clear)
BEGIN
IF (preset = ‘1’) THEN
state <= P_STATE; --or preset state
ELSIF (clear = ‘1’) THEN
state <= INIT; or state for clear
ELSIF (clk = ‘1’ AND clk’event) THEN
– was a rising edge
state <= next_state;
END PROCESS;
F/F with asynchronous preset and clear.
10/8/08
ECE Lecture 8

15. Features of F/F Process
Will set to the correct state for PRESET and/or CLEAR being asserted (active low signals)
If PRESET and CLEAR are both asserted at the same time priority is to PRESET the F/F.
Could be modified to CLEAR the F/F.
Only changes state on the rising clock edge.
For a falling edge it would be
ELSIF (clk = ‘1’ AND clk’event) THEN
10/8/08
ECE Lecture 8

16. Sequential Language Structures
IF STATEMENT
if condition then sequence_of_statements
{elsif condition then sequence_of_statements}
[else sequence_of_statements]
end if;
IF a=‘1’ THEN y<=q;
ELSIF b=‘1’ THEN y<=z AFTER 4 NS;
ELSE y <= ‘0’;
END IF;
10/8/08
ECE Lecture 8

17. Case Statement CASE STATEMENT case expression is
when choices => sequence_of_statements;
end case;
CASE state IS
WHEN “00” => state <= “01”;
WHEN “01” => state <= “10”;
WHEN others => state <= “11”;
END CASE;
10/8/08
ECE Lecture 8

18. Signal Assignment Statements
Used for assignment of state
state <= next_state
Also have binary logic
Have X, Y, and Z as signal of TYPE BIT
Z <= X or Y; Z <= X and Y;
Z <= X nor Y; Z <= X nand Y;
Z <= X xor Y; Z <= X xnor Y;
X <= not Y;
Can use ( ) ‘s for more complex binary logic equations
10/8/08
ECE Lecture 8

19. Language structures not typically used for FSMs
More complex WAIT statements or WAIT statements on complex conditions
Variables
Procedure Calls
Assertion Statements
Loops
Next and Exit statements
RETURN statement which is used in procedures and functions
Null statement
10/8/08
ECE Lecture 8

20. A complete view of the T-Bird FSM
The I/O interface of the controller
ENTITY tl_cntrlr IS
PORT ( rts,lts, haz : IN BIT;
clk : IN BIT;
lc, lb, la : OUT BIT;
rc, rb, ra : OUT BIT);
END tl_cntrlr;
10/8/08
ECE Lecture 8

21. T-BIRD FSM Start the ARCHITECTURE
ARCHITECTURE state_machine OF tl_cntrlr IS
TYPE state_type IS (idle,l1,l2,l3,r1,r2,r3,lr3);
SIGNAL state, next_state : state_type;
BEGIN
--specify F/F process
PROCESS
wait until clk=‘1’ AND clk’event;
state <= next_state;
END PROCESS;
10/8/08
ECE Lecture 8

22. The Next State Process PROCESS (state, lts, rts, haz) BEGIN
CASE state IS
WHEN idle =>
IF (haz=‘1’ OR (lts=‘1’ AND rts=‘1’))
THEN next_state <= lr3;
ELSIF (haz=‘0’ OR (lts=‘0’ AND rts=‘1’))
THEN next_state <= r1;
ELSIF (haz=‘0’ OR (lts=‘1’ AND rts=‘0’))
THEN next_state <= l1;
ELSE next_state <= idle;
END IF;
10/8/08
ECE Lecture 8

23. Next State Proces Continued
WHEN l1 =>
IF (haz = ‘1’) then next_state <= lr3;
ELSE next_state <= l2;
END IF;
WHEN l2 =>
ELSE next_state <= l3;
WHEN l3 => next_state <= idle;
10/8/08
ECE Lecture 8

24. Next State Proces Continued
WHEN r1 =>
IF (haz = ‘1’) then next_state <= lr3;
ELSE next_state <= r2;
END IF;
WHEN r2 =>
ELSE next_state <= r3;
WHEN r3 => next_state <= idle;
WHEN lr3 => next_state <= idle;
END CASE;
END PROCESS;
10/8/08
ECE Lecture 8

25. The Output Process -- State Machine Output Process (Moore Machine)
BEGIN
CASE (state) IS
WHEN idle => lc<=‘0’;lb<=‘0’; la<=‘0’; ra<=‘0’; rb<=‘0’; rc<=‘0’;
WHEN l1 => lc<=‘0’;lb<=‘0’; la<=‘1’; ra<=‘0’; rb<=‘0’; rc<=‘0’;
WHEN l2 =>lc<=‘0’;lb<=‘1’; la<=‘1’; ra<=‘0’; rb<=‘0’; rc<=‘0’;
WHEN l3 => lc<=‘1’;lb<=‘1’; la<=‘1’; ra<=‘0’; rb<=‘0’; rc<=‘0’;
WHEN r1 => lc<=‘0’;lb<=‘0’; la<=‘0’; ra<=‘1’; rb<=‘0’; rc<=‘0’;
WHEN r2 => lc<=‘0’;lb<=‘0’; la<=‘0’; ra<=‘1’; rb<=‘1’; rc<=‘0’;
WHEN r3 => lc<=‘0’;lb<=‘0’; la<=‘0’; ra<=‘1’; rb<=‘1’; rc<=‘1’;
WHEN lr3 => lc<=‘1’;lb<=‘1’; la<=‘1’; ra<=‘1’; rb<=‘1’; rc<=‘1’;
END CASE;
END PROCESS;
END state_machine;
10/8/08
ECE Lecture 8

26. From a state Table
Had a state table
10/8/08
ECE Lecture 8

27. The VHDL Entity Start with the inputs and outputs ENTITY ex_1_fsm IS
PORT ( x,y : IN BIT;
clk : IN BIT;
fsm_out : OUT BIT);
END ex_1_fsm;
10/8/08
ECE Lecture 8

28. The ARCHITECTURE ARCHITECTURE fsm OF ex_1_fsm IS
TYPE state_type IS (s0,s1,s2,s3);
SIGNAL state, next_state : state_type;
BEGIN
-- the F/F Process
PROCESS
wait until clk=‘1’ AND clk’event;
state <= next_state;
END PROCESS;
10/8/08
ECE Lecture 8

29. The Next State Process PROCESS (state,x,y) BEGIN CASE state IS
WHEN s0 => IF (x=‘1’ AND y=‘1’) THEN next_state <= s2;
ELSIF (x /= y) THEN next_state <= s1;
END IF;
WHEN s1 => IF (x=‘1’ AND y=‘1’) THEN next_state <= s3;
ELSIF (x /= y) THEN next_state <= s2;
WHEN s2 => IF (x=‘1’ AND y=‘1’) THEN next_state <= s0;
ELSIF (x /= y) THEN next_state <= s3;
WHEN s4 => IF (x=‘1’ AND y=‘1’) THEN next_state <= s1;
ELSIF (x /= y) THEN next_state <= s0;
END CASE;
END PROCESS;
10/8/08
ECE Lecture 8

30. The Output Process PROCESS (state) BEGIN CASE state IS
WHEN s0 => fms_out <= ‘1’;
WHEN s1 => fms_out <= ‘0’;
WHEN s2 => fms_out <= ‘0’;
WHEN s4 => fms_out <= ‘0’;
END CASE;
END PROCESS;
END fsm; end the architecture
10/8/08
ECE Lecture 8

31. Another Example
Had this state table
10/8/08
ECE Lecture 8

32. The Entity Start with the inputs and outputs ENTITY ex2fsm IS
PORT ( x : IN BIT;
clk : IN BIT;
unlk,hint : OUT BIT);
END ex2fsm;
10/8/08
ECE Lecture 8

33. The Architecture ARCHITECTURE fsm OF ex2fsm IS
TYPE state_type IS (A,B,C,D,E,F,G,H);
SIGNAL state, next_state : state_type;
BEGIN
-- the F/F Process
PROCESS
wait until clk=‘1’ AND clk’event;
state <= next_state;
END PROCESS;
10/8/08
ECE Lecture 8

34. The Next State Process PROCESS (state,x) BEGIN CASE state IS
WHEN A => IF (x=‘0’) THEN next_state <= B; --have 0
ELSE next_state <= A; END IF;
WHEN B => IF (x=‘0’) THEN next_state <= B;
ELSE next_state <= C; END IF;
WHEN C => IF (x=‘0’) THEN next_state <= B;
ELSE next_state <= D; END IF;
WHEN D => IF (x=‘0’) THEN next_state <= E;
ELSE next_state <= A; END IF;
WHEN E => IF (x=‘0’) THEN next_state <= B;
ELSE next_state <= F; END IF;
WHEN F => IF (x=‘0’) THEN next_state <= B;
ELSE next_state <= G; END IF;
WHEN G => IF (x=‘0’) THEN next_state <= E;
ELSE next_state <= H; END IF;
WHEN H => IF (x=‘0’) THEN next_state <= B;
ELSE next_state <= A; END IF;
END CASE;
END PROCESS
10/8/08
ECE Lecture 8

35. The Output Process PROCESS (state,x) BEGIN CASE state IS
WHEN A => unlk <= ‘0’; IF (x=‘0’) THEN hint <= ‘1’;
ELSE hint <= ‘0’; END IF;
WHEN B => unlk <= ‘0’; IF (x=‘1’) THEN hint <= ‘1’;
WHEN C => unlk <= ‘0’; IF (x=‘1’) THEN hint <= ‘1’;
WHEN D => unlk <= ‘0’; IF (x=‘0’) THEN hint <= ‘1’;
WHEN E => unlk <= ‘0’; IF (x=‘1’) THEN hint <= ‘1’;
WHEN F => unlk <= ‘0’; IF (x=‘1’) THEN hint <= ‘1’;
WHEN G => unlk <= ‘0’; IF (x=‘1’) THEN hint <= ‘1’;
WHEN H => IF(x=‘0”) THEN unlk <= ‘1’; hint = ‘1’; ELSE unlk=‘0’; hint=‘0’; END IF;
END CASE;
END PROCESS;
END fsm; end the architecture
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