1. Office Hours: M, W 12:30 to 2:30 PM or By Appointment
Villanova University Department of Electrical and Computer Engineering   ECE 3450 Digital Electronics Fall 2017
Dr. Mark A. Jupina
430 Tolentine Hall
(610) 519 – 7561
Office Hours: M, W 12:30 to 2:30 PM or By Appointment
ECE M. A. Jupina, VU, 2017

2. ECE 3450 Course Rationale
Provide our students with additional experience in prototyping and troubleshooting digital board-level and on-chip applications.
Students gain additional hardware experience before the implementation of their senior capstone project.
ECE M. A. Jupina, VU, 2017

3. Introduction Syllabus Practicums and Projects
ECE M. A. Jupina, VU, 2017

4. Some Examples of Practicums and Projects
ECE M. A. Jupina, VU, 2017

5. Hierarchical Structure and Design Approach
Digital
Design
Projects
Buses, Clocks, Memory, and FSMs
Properties of Digital Circuits
Synthesis and Simulation Software
Design
Simulation
Prototyping
Testing
ECE M. A. Jupina, VU, 2017

6. Properties of Digital CircuitsV DD
Gnd
74LS04
and
CD4069
Measurements are performed on both a TTL and CMOS inverter.
Properties Measured: VTC, noise margins, power supply current (power dissipation) versus frequency, propagation delay, and power-delay product.
LS-TTL vs CMOS properties
PART I: Voltage Transfer Characteristics
Voltage ramp is used to sweep out the VTC in the x-y mode on a scope. Voltage levels and noise margins determined graphically.
PART II: Power Supply Current and Power Dissipation
Square wave excitation at different frequencies and capacitive loading is applied while power supply current is measured. Average power dissipation as a function frequency is determined.
PART III: Average Propagation Delay Time and Power-Delay Product
A three-inverter ring oscillator circuit is used to measure average propagation delay. Power delay product (a benchmark to compare technologies) is calculated at 1 MHz for these old LS-TTL and CMOS technologies.
ECE M. A. Jupina, VU, 2017

7. Properties of Digital Circuits
PART I: Voltage Transfer Characteristics and Noise Margins
chan chan 2
Measurements are performed on both a TTL and CMOS inverter.
LS-TTL vs CMOS properties
PART I: Voltage Transfer Characteristics
Voltage ramp is used to sweep out the VTC in the x-y mode on a scope. Voltage levels and noise margins determined graphically.
74LS04
CD4069
ECE M. A. Jupina, VU, 2017

8. Properties of Digital Circuits
PART II: Power Supply Current and Power Dissipation
VDD
ISUPPLY C
Measurements are performed on both a TTL and CMOS inverter.
LS-TTL vs CMOS properties
PART II: Power Supply Current and Power Dissipation
Square wave excitation at different frequencies and capacitive loading is applied while power supply current is measured. Average power dissipation as a function frequency is determined.
ECE M. A. Jupina, VU, 2017

9. Properties of Digital Circuits
PART III: Average Propagation Delay Time and Power-Delay Product
channel 1
Measurements are performed on both a TTL and CMOS inverter.
LS-TTL vs CMOS properties
PART III: Average Propagation Delay Time and Power-Delay Product
A three-inverter ring oscillator circuit is used to measure average propagation delay. Power delay product (a benchmark to compare technologies) is calculated at 1 MHz for these old LS-TTL and CMOS technologies.
74LS04
CD4069
ECE M. A. Jupina, VU, 2017

10. Layout of a CMOS Circuit
Microwind CAD Generated Drawing
“Stick” Drawing in Power Point
The CAD layout of an AND gate on the left was generated using the compile function in the Microwind 2.6a software. Note: PMOS transistors are larger than the NMOS transistors (Wp = 3 Wn).
The PMOS transistors (P+ source and drain regions shown in brown) are placed in a n-well or n-tub region (shown in green). The NMOS transistors (N+ source and drain regions shown in green) are placed in a p-type substrate (no p-well or p-tub region) and therefore the p-type substrate is not shown in this depiction.
A similar layout of an AND gate is shown in the drawing on the right. This was drawn in Power Point. Sizing of the transistors is not done in this “stick diagram” representation.
ECE M. A. Jupina, VU, 2017

11. The Altera DE2 Development Board
ECE M. A. Jupina, VU, 2017

12. SignalTap II Embedded Logic Analyzer (Altera DE2 Board)
The SignalTap II logic analyzer captures and displays real-time signal behavior in a system on a programmable chip (SOPC), giving engineers the ability to observe interactions between hardware and software in their system designs. Available in the Quartus II software, the SignalTap II logic analyzer supports the highest number of channels, sample depth, and clock speeds of any embedded logic analyzer in the programmable logic market. The Quartus II software also provides designers with a graphical interface to define custom-trigger-condition logic to provide greater accuracy and enhances the ability to isolate problems. The above figure shows the components of the SignalTap II embedded logic analyzer. The SignalTap II embedded logic analyzer does not require any external probes or changes to user design files to capture a design's state of internal nodes or I/O pins.
ECE M. A. Jupina, VU, 2017

13. Required Installation of Quartus II on Laptops
Go to the facultypublic-sa drive on the \\egrstorage network, find the ece3450 folder, and download the executable file 91_quartus_free to your laptop’s hard drive. Install the Quartus II software.
Version 9.1 has a built-in simulation tool. Versions 10 and later require the use of a third party simulation tool, such as ModelSim.
After Installation, run the Quartus II software. Go to the menu Tools, License Setup, and in the box for License File put the following so that your laptop can find the license on the ECE server.
Install this software before the Quartus II tutorial lab.
ECE M. A. Jupina, VU, 2017

14. Design Process for Schematic or VHDL Entry
ECE M. A. Jupina, VU, 2017

15. Quartus II Tutorial
ECE M. A. Jupina, VU, 2017

16. Sonar Sensor Project (Module Interfaced to a Simple Processor on the Altera Board)
Polaroid sensor range is six inches to 35 feet
16 cycles at 49KHz
Listen for return pattern
Sound travels ~0.9 ms/ft
Timer and Decoder on
DE2 determines distance
ALU determines speed
Sensor
Where do we go after implementing a simple processor design with a state machine?
You will add a sonar sensor to the simple processor.
Polaroid 6500 Sonar Ranging Module - Measure position and speed of a person standing up to at least 10 feet away from the sensor
Position resolution: inches or cm and Velocity resolution: in/s (ft/s) or cm/s (dm/s, m/s)
The overall goal of the sensor design project is to interface a sonar sensor to the DE2 board and display sensed information, such as the position and velocity of a person, on the seven segment displays on the DE2 board.
ECE M. A. Jupina, VU, 2017

17. Block Diagram of Sonar Sensor Project
SONAR SYSTEM
PROCESSOR
Data Request
FSMs
Data Ready
Y-bits
Sonar
Circuit
Data Bus
Registers
ALU
DATA
Sonar system contains the sensor, sensor support circuitry, and the “Sonar Circuit” that resides on the DE2 board. The sonar circuit contains a counter circuit that captures the time it takes for an ultrasonic signal to travel from and back to the sensor. This X-bit count value will also be converted into a Y-bit position value by a shift circuit or a divider circuit that resides within the Sonar Circuit.
The Processor will be responsible for the control (FSMs), data storage (current and previous position and current velocity), and the calculation of the velocity of an object in front on the sensor.
To transmit data between the systems, it is often necessary to provide what are called “handshaking” signals (Data Request and Data Ready) that ensure that the data is received correctly, particularly when the two systems are running at very different speeds. Consider the situation above, in which Y-bits of data are to be transmitted from the Sonar System to the Processor.
ECE M. A. Jupina, VU, 2017