1. Defining Statistical Sensitivity for Timing Optimization of Logic Circuits with Large-Scale Process and Environmental Variations
Xin Li, Jiayong Le, Mustafa Celik
Extreme DA, 165 University Avenue, Palo Alto, CA 94301
Lawrence Pileggi
Dept. of ECE, Carnegie Mellon University, Pittsburgh, PA 15213
Title: Defining statistical sensitivity for timing optimization of logic circuits with large-scale variations
Purpose of this work: Explore how to use the results from statistical timing to guide statistical optimization

2. Overview Introduction Statistical sensitivity Sensitivity evaluation
Numerical examples
Conclusion

3. Process Variations (3σ / Nominal) [Nassif 01]
IC Technology Scaling
Feature Size
Scale Down
0.35 μm
0.18 μm
90nm
Process Variations (3σ / Nominal) [Nassif 01]
Feature size decrease, absolute variation does not decrease as fast, relative variation increases
Process variations become increasingly large!

4. Intra-die variations become increasingly important!
Process Variations
Examples of variations
Gate length & width
Threshold voltage
metal width & thickness
ILD (inter-layer dielectric)
Front-end Variations
Back-end Variations
Intra-Die
Process variations have complicated sources …
Intra-die variation is becoming important
Inter-Die
Intra-die variations become increasingly important!

5. Corner-Based Analysis
Pessimistic results for statistical variation
Variations are not fully correlated
Parameter corners are not necessarily performance corners x1 x2
Corners 6σ y
12σ
8.48σ
1. Corner case analysis work on process corners
2. Parameter corner are not necessarily to be the performance corner
Cell
Wire

6. Corner-Based Analysis
Cannot handle on-chip variation (OCV)
Independence between capturing clock and data path
On-chip cell variation at different location
Independent wire variations on different metal layer ?
On chip variations, cell and wire
Delay variation from launch clock path + data path and capture clock path can be independent
3. Heuristics: Derate, Clock Uncertainty

7. Statistical Timing Analysis
Delays and arrival times are described as random variables
ΔVTH ΔL
Statistical timing analysis is getting a lot of attentions
Delays and Arrival times are modeled as random variables
Propagated through timing graph to calculate final statistical delay or slack

8. Statistical Timing Analysis
Critical path is not well defined
Each path has certain probability to be critical
In nominal case, people use slack and critical path to guide optimization
However, with process variation, it is no longer straightforward to use critical path and slack for circuit optimization

9. Statistical Timing Analysis
Slacks are correlated random variables
Difficult to compare two slacks
Both mean and variances are important
Cannot use individual slacks to determine timing yield
Correlations are important
PDF N2 N1
Slack

10. Statistical Timing Analysis
Question I
How to find “critical” path/arc/node under process variations?
Question II
How to provide new criteria to help statistical design/optimization?
To do variation-aware optimization, we have to solve two fundamental problems.

11. Overview Introduction Statistical sensitivity Sensitivity evaluation
Numerical examples
Conclusion
In the second part of this presentation, I will introduce the definition of statistical sensitivity and how to use it to guide statistical optimization.

12. Path Sensitivity In nominal case Total delay equals
D is the total delay
Pi is the delay of i-th path
Define path sensitivity
Critical path is important since it has nonzero sensitivity
1. First, here we introduce the concept of path sensitivity…
2. In nominal cases, critical path is important because it determined the circuit delay.

13. Path Sensitivity In statistical case Define path sensitivity
D and Pi are random variables
E{▪} denotes the expectation of random variables
If any two paths are not exactly identical, we can prove
SPathPi is equal to the probability that Pi is the critical path
Pick up most critical paths based on SPathPi
In statistical cases, path delays and circuit delay are random variables, the path sensitivity can be defined using their expectation values.

14. Path Sensitivity
Statistical critical path is not efficient for optimization
The number of competing path increases exponentially
Path delays are statistically correlated
We need new criteria to guide optimization
Now, we defined path sensitivities and explained how to use sensitivity to identify critical path.
However, statistical critical path is not efficient for circuit optimization.

15. Arc Sensitivity In nominal case Define arc sensitivity
D is the total delay
Pi is the delay of i-th path
Am is the delay of m-th arc
Only arcs on critical path have nonzero sensitivity
All arcs in critical path are equally important for timing optimization
1 iff critical path
1 iff Am in Pi
Instead of working on path, we work on arcs
In nominal case, we define arc sensitivity as the total circuit delay change w.r.t arc delay change.
Explain …
Highlight two small items

16. Arc Sensitivity In statistical case Define arc sensitivity
D and Pi and Am are random variables
E{▪} denotes the expectation of random variables
If any two paths are not exactly identical, we can prove
SArcAm is equal to the probability that Am sits on critical path
SArcAm provides a criterion to select most critical arcs for optimization
1. Similar as path sensitivity, we can also define arc sensitivity using their expectation values
2. And we define critical arc as the arc that has maximal arc sensitivities
3. By definition, reducing delay of critical arc can effectively reduce the total delay

17. Node Sensitivity In nominal case Define node sensitivity
D is the total delay
Pi is the delay of i-th path
Nk is the arrival time of k-th node
Only nodes on critical path have nonzero sensitivity
All nodes in critical path are equally important for timing optimization
1 iff critical path
1 iff Nk in Pi

18. Node Sensitivity In statistical case Define node sensitivity
D and Pi and Nk are random variables
E{▪} denotes the expectation of random variables
If any two paths are not exactly identical, we can prove
SNodeNk is equal to the probability that Nk sits on critical path
SNodeNk provides a criterion to select most critical nodes for optimization

19. Slack Sensitivity Sensitivity considering clock tree S < 0 S = 0
Positive sensitivities on launching clock + data path
Negative sensitivity on capturing clock path
Zero sensitivity on common clock path
S < 0
S = 0
S > 0
Till now, we only focus on arc sensitivities for combinational block.
Actually arc sensitivities have some interesting features if we also include clock tree and define the sensitivity w.r.t slacks, instead of arrival.
CPPR

20. Overview Introduction Statistical sensitivity Sensitivity evaluation
Numerical examples
Conclusion

21. Statistical Timing Analysis
First-order block-based statistical timing analysis
In first order statistical timing analysis, arrival times are modeled as a linear function of independent normal random variables.
Once these base variables are defined, arrival times can be uniquely represented through a set of coefficients.
Independent random variables with normal distribution
Unique representation for each arrival time
Basis of random variables

22. Statistical Sensitivity Analysis
First-order sensitivity matrix representation
Under this notion, the change in arrival times can also be represented as the changes on these coefficients.
Further more, if we have two arrival times x and z, their relationship of delta change can be represented using the sensitivity matrix as shown here.

23. Atomic Operation Add(▪) Max(▪) x Ay x z z y
SBasis is a complex function, but has analytic expression
SBasis is identity matrix

24. Sensitivity Propagation
Propagate from output to input using breadth-first traversal Q
Out Ak Pk
Once basic operations are defined, we can do a breadth-first backward traversal to determine the sensitivity of final output delay w.r.t individual arc delays
Here is a simple example.
Assume we already calculated the sensitivity of output arrival w.r.t arrival pk, to calculate the sensitivity of output w.r.t arrival Ak, we can first calculate the sensitivity of Pk with respect to arrival (Q+Ak) using Max operation. Then we can calculate the sensitivity of (Q+Ak) w.r.t Ak using Add operation.
To calculate the sensitivity of output w.r.t arrival time Q, we only need to apply chain rule to add up sensitivities from different paths.
Determined in previous step during traversal
Determined by Max(▪)
Determined by Add(▪)

25. Overview Introduction Statistical sensitivity Sensitivity evaluation
Numerical examples
Conclusion

26. Circuit schematic of a simple logic circuit
A Simple Example
Synthesized in a commercial CMOS 0.13m process
Consider inter-die/intra-die variations on VTH0, TOX, W and L
Circuit schematic of a simple logic circuit

27. Comparison on estimated sensitivity values
A Simple Example
Compared with Monte Carlo analysis, the proposed sensitivity analysis error is less than 1.6%
Arc
Proposed MC
<I3,N2>
100%
<N2,N3>
99.9%
<N2,N4>
0.1%
<N3,N5>
70.8%
72.4%
<N3,N6>
29.1%
27.5%
<N4,N6>
<CK,N7>
<N7,N8>
<N7,N9>
29.2%
27.6%
Accurate
I3->N2 go through 3 paths, that’s why it has big sensitivity
Comparison on estimated sensitivity values

28. Computation Time (Sec.)
ISCAS’85 Circuit
CKT
Sensitivity Error
Computation Time (Sec.)
Min
Avg
Max
Proposed MC
Timing
Sensitivity
c432
0.0%
0.1%
1.6%
0.01
128
c499
2.4%
0.02
154
c880
0.9%
1.3%
0.03
281
c1355
0.4%
2.5%
0.05
359
c1908
3.4%
0.07
0.06
504
c2670
0.3%
2.6%
0.09
771
c3540
0.11
974
c5315
0.8%
1.8%
2.8%
0.17
1381
c6288
0.6%
1.9%
0.25
1454
c7552
0.7%
1.1%
3.5%
0.26
0.14
1758
less than 3.5% error for all circuits
the proposed sensitivity analysis achieves about 4000x speedup over the Monte Carlo simulation
In addition, the sensitivity analysis time is slightly less than the timing analysis time

29. Slack & Sensitivity Wall
Optimize C7552 under nominal process condition
Nominal timing analysis shows that many slacks are equally important !
Statistical sensitivity analysis shows that only a few arcs dominate the timing performance !
Slack wall is steep
Sensitivity distribution is flat

30. Large Industry Examples
Computation cost scales linearly in circuit size
Design
# of Cells
# of Pins
Computation Time (Sec.)
Timing
Sensitivity A
1.6  104
6.2  104
2.4
1.9 B
6.0  104
2.2  105
7.2
5.17 C
3.3  105
1.3  106
92.6
75.6
Circuit size and statistical timing/sensitivity analysis cost
The computation cost of the proposed sensitivity analysis scales linearly as the circuit size increases

31. Conclusion
Propose a sensitivity framework to evaluate the importance of each path/arc/node
Theoretically prove the equivalence between sensitivity and probability
Develop a practical algorithm to compute sensitivities
Linear complexity in circuit size
Incremental analysis for timing optimization