1. Scientific Contributions
N-tier design
methodology
Complete physical models
for distributed rlc interconnects
Repeater insertion
in n-tier design
Compact unified models for
delay, crosstalk & repeaters
Optimal aspect ratios
for multilevel int. arch.
Effects of inductance
on multilevel int. arch.
MINDS

2. List of Publications Conference papers :
R.Venkatesan, J.A.Davis and J.D.Meindl, Performance enhancement through optimal n-tier multilevel interconnect architectures, Proc. ASIC/SOC conference, Washington DC, Sept , pp
J.A.Davis, R.Venkatesan, K.A.Bowman and J.D.Meindl, Gigascale integration (GSI) interconnect limits and n-tier multilevel interconnect architectural solutions, Proc. SLIP, San Diego, April , pp
R.Venkatesan, J.A.Davis, K.A.Bowman and J.D.Meindl, Optimal repeater insertion for n-tier multilevel interconnect architectures, Proc. IITC, San Francisco, June , pp
R.Venkatesan, J.A.Davis, K.A.Bowman and J.D.Meindl, Minimum power and area n-tier multilevel interconnect architectures using optimal repeater insertion, Proc. ISLPED, Rapallo/Portofino Coast, Italy, July , pp
J.D.Meindl, R.Venkatesan, J.A.Davis, J.W.Joyner, A.Naeemi, P.Zarkesh-Ha, M.Bakir, T.Mule, P.A.Kohl and K.P.Martin, Interconnecting device opportunities for gigascale integration (GSI), Proc. IEDM, Washington D.C., Dec 2001, pp
R.Venkatesan, J.A.Davis and J.D.Meindl, A complete physical model for distributed RLC interconnects - transient voltage, time delay and crosstalk, Proc. DAC, New Orleans, June 2002, pp
A.Naeemi, R.Venkatesan and J.D. Meindl, System-on-a-chip global interconnect optimization, Proc. ASIC/SOC Conference, Rochester, NY, Sept 2002, pp
R.Venkatesan, J.A.Davis and J.D.Meindl, Time delay, crosstalk and repeater insertion models for high performance SOC’s, Proc. ASIC/SOC Conference, Rochester, NY, Sept 2002, pp
J.Joyner, R.Venkatesan, J.A.Davis and J.D.Meindl, The limits of system improvement through liquid diagonal routing of interconnects, submitted to IITC, San Francisco, CA, June 2003.
R.Venkatesan, J.A.Davis and j.D.Meindl, Optimal aspect ratios for GSI multilevel interconnect architectures, to be submitted to ASIC/SOC Conf., Portland, OR, Sep

3. List of Publications Journal papers : Book chapter :
J.A.Davis, R.Venkatesan, A.Kaloyeros, M.Bylansky, S.J.Souri, K.Banerjee, K.C.Saraswat, A.Rahman, R.Reif and J.D.Meindl, Interconnect limits on Gigascale integration (GSI) in the 21st century, Proceedings of the IEEE - special issue on limits to semiconductor technology, Vol. 89, No. 3, March 2001, pp
R.Venkatesan, J.A.Davis, K.A.Bowman and J.D.Meindl, Optimal n-tier multilevel interconnect architectures for gigascale integration, IEEE Transactions on VLSI Systems - special issue on System Level Interconnect Prediction, Vol. 9, No. 6, Dec 2001, pp
J.W.Joyner, R.Venkatesan, P.Zarkesh-Ha, J.A.Davis and J.D.Meindl, Impact of three dimensional architectures on homogenous digital circuits , IEEE Transactions on VLSI Systems - special issue on System Level Interconnect Prediction, Vol. 9, No. 6, Dec 2001, pp
R.Venkatesan, J.A.Davis and J.D.Meindl, A complete physical model for distributed rlc interconnects with capacitive load – Part 1 : Single line transients and coupled line crosstalk, to be published in IEEE Transactions on Electron Devices.
R.Venkatesan, J.A.Davis and J.D.Meindl, A complete physical model for distributed rlc interconnects with capacitive load – Part 2 : Unified models for time delay, crosstalk and repeater insertion, to be published in IEEE Transactions on Electron Devices.
A.Naeemi, R.Venkatesan and J.D.Meindl, Optimal global interconnecting devices for Gigascale Integration, to be published in IEEE Transactions on Electron Devices.
Book chapter :
J.A.Davis and J.D.Meindl, Interconnect design issues and opportunities for Gigascale Integration, Kluwer Academic Publishers, in press.