1. Student Meeting Jose Luis Sirvent PhD. Student 17/02/2014
Beam Secondary Shower Acquisition System: Starting to implement GBT Protocol in Igloo2 and FATALIC as readout candidate
Student Meeting
Jose Luis Sirvent
PhD. Student
17/02/2014

2. Topics of this presentation
1. GBT-FPGA:
A general overview and introduction to my current work.
2. Igloo2 Dev. Kit:
Issues, testing and GBT protocol implementation status.
3. FATALIC ASIC:
Some comments and plans for ASIC evaluation.

3. GBT-FPGA Some information and resources
GBT-Protocol implementation on FPGAS for GBTx communication & Emulation:
Public SharePoint:
Public SVN Releases (old):
Mailing List:
Contacts for support: ,
Last news:
PH-ESE Repository (last updates):
Indico Follow-up (GBT-FPGA):
Support & code available for (Dev. Kits):
Xilinx Virtex 5 / 6 / 7 & Kinex 7 …
Altera Cyclone V & Statrix V…
Microsemi: Smatrfusion2, Igloo2 ??? At least not yet… but makes sense (CMS, MOPOS, us…)
Two Versions:
Standard (STD)  Data Readout (DAQ)
Low and Deterministic latency (LATOP) FE control & Time, Trigger and control (TTC)
First Release 2011
First Release March 2014

4. GBT-FPGA The Basic concept (Modular design)
GBT-FPGA Firmware Starter Kit for Altera and Xilinx devices. Sophie Baron CERN/PH/ESE. GBT-FPTA Starter kit user guide V0.1
* Vendor Specific Modules (IP Cores)

5. GBT-FPGA The Basic concept (Clocking Scheme and TTC clock recovery)
GBT-FPGA Comments on deterministic latency and recommendations to handle optimization schemes. Sophie Baron, PH/ESE. 2011

6. GBT-FPGA Current Status (Latency optimization)
GBT-FPGA One unified core for multiple users. Manoel Barros Marin, PH/ESE/BE Students-Fellows seminar (05/02/2014).

7. GBT-FPGA The code and the work I’m carrying out
For the moment I’ll migrate with the old STD version and only GBT frame (simplest), once done, tested and well understood, I’ll move to LATOP version.

8. Igloo2 Development Kits They arrived really quickly
Quite a lot of motivation to start
Know-how base given by “Comprehensive VHDL Course”
Time to hands-on-work
Put into practice newly acquired knowledge
Good design resources:
Examples, demos, application notes
A lot of documentation:
Some is shared with SmartFusion2 (makes it cofusing)
Many software updates
Reading / Understanding is a big part

9. Igloo2 Development Kits They arrived really quickly (But not in the best conditions…)
Defect discovered by chance:
During first SERDES testing
Track TXD2N Damaged!

10. Igloo2 Development Kits They arrived really quickly (But not in the best conditions…)
Defect discovered by chance:
During first SERDES testing
Track TXD2N Damaged!
Reparation of
damaged track!!
Many thanks to William for his help during the reparation!!
Microscope
Soldering tools
Advice…

11. Igloo2 GBT-FPGA (STD) implementation status Substitute Xilinx IP’s by Microsemi IP’s (Some are straighforward)

12. Igloo2 GBT-FPGA (STD) implementation status Substitute Xilinx IP’s by Microsemi IP’s (Others.. not)
Transceiver with 4.8GBPS:
- A lot of configuration registers
- Big amount of documentation
- Different implemented protocols (not needed)
- Power-Up Initialization needed (HPMS)
- Synchronization issues
- Needed standalone testing and verification

13. Igloo2 SERDES Testing (Tx part) Different Speeds & Configurations
Scope not for eye diagram determination BW 1Ghz, used just for reference  2* Signal Freq = Bit rate
Transmission pattern  “ ”
1.25Gbps
Pre-Configured
**EPCS : External Physical Coding Sublayer

14. Igloo2 SERDES Testing (Tx part) Different Speeds & Configurations
Scope not for eye diagram determination BW 1Ghz, used just for reference  2* Signal Freq = Bit rate
Transmission pattern  “ ”
1.25Gbps
Pre-Configured
2.5Gbps
Pre-Configured
**EPCS : External Physical Coding Sublayer

15. Igloo2 SERDES Testing (Tx part) Different Speeds & Configurations
Scope not for eye diagram determination BW 1Ghz, used just for reference  2* Signal Freq = Bit rate
Transmission pattern  “ ”
1.25Gbps
Pre-Configured
2.5Gbps
Pre-Configured
4.8Gbps!!
Custom Parameters
**EPCS : External Physical Coding Sublayer

16. Igloo2 SERDES Testing (EPCS-4
Igloo2 SERDES Testing (EPCS-4.8Gbps) Looping the lines, TX & RX simulation and start-up sequence

17. Igloo2 SERDES Testing (EPCS-4
Igloo2 SERDES Testing (EPCS-4.8Gbps) Looping the lines, TX & RX simulation and start-up sequence
Next Step:
Continue validation or data TX/RX in simulations
Start validation with Igloo2 Dev. Kit (Lane1)
Study initialization sequence and look for optimization
Gradual implementation of IP module on Igloo2 GBT-FPGA code
Frame Alignment
GBT encoding/decoding …

18. FATALIC3 Some comments: Looking for a PlanB option for pCVD readout ASIC (QIE10 is our PlanA)
Some specifications:
3 Gain Ranges (1,8,64)
Dynamic Range: 12fC – 1.2nC (4e4)
Input Impedance: 1 ohm
RadHard: IBM130nm Technology
Differential Vout
Designed for ATLAS TILECAL Upgrade.
Direct competition with QIE10.
Final ASIC will contain integrated ADC’s (TACTICs)
Meeting with Nicolas Pillet (Designer):
-- Detailed meeting minutes available on-line --
-- Very kind and helpful, happy to provide some samples for testing
-- He even provided/developed an internal note (instructions manual) !!

19. FATALIC3 Some comments: Looking for a PlanB option for pCVD readout ASIC (QIE10 is our PlanA)
Some specifications:
3 Gain Ranges (1,8,64)
Dynamic Range: 12fC – 1.2nC (4e4)
Input Impedance: 1 ohm
RadHard: IBM130nm Technology
Differential Vout
Designed for ATLAS TILECAL Upgrade.
Direct competition with QIE10.
Final ASIC will contain integrated ADC’s (TACTICs)
Meeting with Nicolas Pillet (Designer):
-- Detailed meeting minutes available on-line --
-- Very kind and helpful, happy to provide some samples for testing
-- He even provided/developed an internal note (instructions manual) !!
We still have some other candidates for this:

20. Beam Secondary Shower Acquisition System
FATALIC3 Test Board Planning the Evaluation of FATALIC for BWS system usability
In_low (64)
In_high (1-8)
Out_A:1
Out_A:8
Out_A:64 6 5 4 3 2 1 44 43 42 41 40 17 16 15 14 13 12 11 10 9 8 7 28 27 26 25 24 23 22 21 20 19 18 39 38 37 36 35 34 33 32 31 30 29
FATALIC3 Test Board
Beam Secondary Shower Acquisition System
Vref: 0.6V
gnd: 0V
vdda: 1.6V
Thanks to N.Pillet for providing the FATALIC3 ASICS and Internal Note for evaluation 

21. Beam Secondary Shower Acquisition System
FATALIC3 Test Board Planning the Evaluation of FATALIC for BWS system usability
In_low (64)
In_high (1-8)
Out_A:1
Out_A:8
Out_A:64 6 5 4 3 2 1 44 43 42 41 40 17 16 15 14 13 12 11 10 9 8 7 28 27 26 25 24 23 22 21 20 19 18 39 38 37 36 35 34 33 32 31 30 29
FATALIC3 Test Board
Beam Secondary Shower Acquisition System
Vref: 0.6V
gnd: 0V
vdda: 1.6V
Thanks to N.Pillet for providing the FATALIC3 ASICS and Internal Note for evaluation 