1. Wed. Sept 20 Announcements
HW/Lab 5 Posted
Lab 5 is done in pairs
HW is probably more intensive than the lab.
Module 1 Clicker Quiz Friday
All module 1 fair game.
Focus on stuff not yet quizzed on.

2. Microcontroller Interfacing
Module 2
Microcontroller Interfacing
Tim Rogers 2017

3. Needs to input/output from other devices
Learning Outcome #2
“An ability to interface a microcontroller to various devices”
Why?
Printer
Temperature sensors
Cameras
Microcontroller cannot live alone
Needs to input/output from other devices
Pressure sensors
Light sensors
External memory
Screen

4. A+B are the most complex interface we will study in 362
Learning Outcome #2
“An ability to interface a microcontroller to various devices”
A+B are the most complex interface we will study in 362
Bus Timing Analysis
9S12C Multiplexed Bus Expansion
General-Purpose I/O Ports
Buffered I/O Handling
Interrupt Handling
Buffered, Interrupt-Driven Printer Design Example
How?

5. High-level Picture of External Memory
Location in memory.
Effective address
Upper-most bits /
Address Decode PLD
Is the chip turned on? 0=on, 1=off
CPU
External
Memory Chip
Chip Enable (CE)
M-bits /
Address Bus (Abus)
Address (in)
N-bits /
Data Bus (Dbus)
Data (in/out)
Bits for the actual value
Should memory output on data bus?
0=yes, 1=no
Is the processor reading (load) or writing (store)
R/W’
Output Enable (OE)
CLK
Write Enable (WE)
Should memory write bits on data bus into itself? 0=yes, 1=no
Bus Clock: Comes from CPU, tells memory when to do stuff.
One cycle=time to do one read or write

6. CPU Timing Parameters Common to READ and WRITE cycles READ cycle
tCY (CPU bus cycle time)
tAD (CPU address generation delay)
tAH (CPU address hold time)
READ cycle
tRS (CPU read data setup time)
tRH (CPU read data hold time)
WRITE cycle
tDD (CPU write data generation delay)
tWH (CPU write data hold time)
tWZ (CPU write data float delay, after tWH)

7. Memory Timing Parameters
READ Cycle
tAA (memory address access time)
tCE (memory chip enable access time)
tOE (memory output enable access time)
tOH (memory output hold time)
tOZ (memory output data float delay, after tOH)
WRITE cycle
tIS (memory input data setup time)
tIH (memory input data hold time)
tAW (memory address to write time)
tCW (memory chip enable to write time)
tWP (memory write pulse width)

8. Signals on the 9S12 you will look at in lab 5
9S12C Bus Signals
Looking ahead…
Signals on the 9S12 you will look at in lab 5

9. Successive Synchronous Read Cycles
CPU wants to read data
i.e. a load instruction
”Successive” = 2 reads, back to back
“Synchronous” = because it is driven by the clock

10. Successive Synchronous Read Cycles
Clock Drives Everything.
CPU Listens to falling edge of clock

11. Successive Synchronous Read Cycles
After falling edge, CPU “thinks”, then initiates read. “Cross-hatch” while signal potentially changes. CPU drives Stable R=1 in green.

12. Successive Synchronous Read Cycles
R/W’
CLK
OE’ is telling the memory when to drive the data bits. This signal goes low when R=1 and CLK=1.

13. Successive Synchronous Read Cycles
CPU Drives the ADDR lines. They become valid at the same time R/W’ does.

14. Successive Synchronous Read Cycles
CE’ depends on ADDR. After ADDR stabilizes, CE’ stabilizes. “Blip” to one here could also just be a “cross-hatch”.
Upper-most bits /
Address Decode PLD
ADDR

15. Successive Synchronous Read Cycles
Be told to output
Have a valid address
Memory Chip drives the data lines.
To supply the data, the chips needs to be…
Turned on
Once all these things are true, it takes some time to “think”, then provides data

16. Successive Synchronous Read Cycles
Where CPU actually reads what’s on the bus
CPU is completely driven by the clock.
Captures what is on the data bus on the falling edge

17. Successive Synchronous Read Cycles
Where CPU actually reads what’s on the bus
tCY
R/W’ takes “Address Delay” time from the falling edge of the clock to become valid
tAD
tAH
R/W’ is held for “Address Hold” time after CPU reads

18. Successive Synchronous Read Cycles
Where CPU actually reads what’s on the bus
For CPU to read properly, data bus must satisfy setup and hold times.

19. Successive Synchronous Read Cycles
Where CPU actually reads what’s on the bus
Setting OE’ to 1 tells the memory to “stop outputting”

20. Successive Synchronous Read Cycles
Where CPU actually reads what’s on the bus
Setting OE’ to 1 tells the memory to “stop outputting”
The memory keeps outputting for “output hold” time
”Output to float delay” is the time where it takes the memory to “get off the data bus.

21. Successive Synchronous Read Cycles
Where CPU actually reads what’s on the bus
The data “absolutely has to be ready” by the Fed-Ex line

22. Successive Synchronous Read Cycles
Where CPU actually reads what’s on the bus
These Yellow segments represent the Maximum values the memory can have and still meet timing requirements

23. Successive Synchronous Read Cycles
Where CPU actually reads what’s on the bus
These Yellow segments represent the Maximum values the memory can have and still meet timing requirements
If the memory is actually quicker, then you get Read timing margin

24. Successive Synchronous Read Cycles
Where CPU actually reads what’s on the bus
The “Green (Fed-Ex) Line” for a READ cycle refers to the instant that the data “absolutely, positively has to be there” (within nanoseconds) for the memory read operation to be successful. The Fed-Ex Line is determined by: A. the read setup time prior to the end of the bus cycle B. the bus cycle minus the address generation delay C. the bus cycle minus the data generation delay D. the read hold time prior to the end of the bus cycle E. none of the above
If the memory is actually quicker, then you get Read timing margin

25. Successive Synchronous Read Cycles
Where CPU actually reads what’s on the bus
If the value on the data bus changes before the “Green (Fed-Ex) Line”: A. bus fighting might occur B. the wrong value might be read by the processor C. data might be read from the wrong address D. the memory chip might be damaged E. none of the above
If the memory is actually quicker, then you get Read timing margin

26. Successive Synchronous Read Cycles
Where CPU actually reads what’s on the bus
If the value on the data bus changes tRS after the “Green (Fed-Ex) Line”: A. bus fighting might occur B. the wrong value might be read by the processor C. data might be read from the wrong address D. the memory chip might be damaged E. none of the above
If the memory is actually quicker, then you get Read timing margin

27. Successive Synchronous Read Cycles
Where CPU actually reads what’s on the bus
The following parameter has no influence on the read timing margin available: A. tAA B. tOE C. tOH D. tCE E. none of the above
If the memory is actually quicker, then you get Read timing margin

28. Successive Synchronous Write Cycles

29. Successive Synchronous Write Cycles

30. Successive Synchronous Write Cycles

31. Successive Synchronous Write Cycles

32. Successive Synchronous Write Cycles

33. Successive Synchronous Write Cycles

34. Successive Synchronous Write Cycles
Where write to memory actually occurs

35. SRAMs
Conceptually, just a D-Flop where clock is controlled by SEL/WR signals

36. Successive Synchronous Write Cycles

37. Successive Synchronous Write Cycles

38. Successive Synchronous Write Cycles

39. Successive Synchronous Write Cycles
tIH is an SRAM parameter.
So – based on SRAM input signals
tWH is a CPU parameter.
So – based on clock edges

40. Successive Synchronous Write Cycles

41. Successive Synchronous Write Cycles
The “Green (Fed-Ex) Line” for a WRITE cycle refers to the instant that the data “absolutely, positively has to be there” (within nanoseconds) for the memory write operation to be successful, which is: A. the write pulse width B. the input setup time prior to the end of the bus cycle C. the input setup time prior to the negation of write enable D. the input hold time following the negation of write enable E. none of the above

42. An Example: CPU timing Specs
Description
Parameter
Value
Bus clock period
tCY
200 ns
Address generation delay
tAD
30 ns
Address hold time
tAH
20 ns
Read setup time
tRS
Read hold time
tRH
Write data generation delay
tDD
80 ns
Write hold time
tWH
Write float delay (after tWH)
tWZ
10 ns
Used on both Read and Write
Read Specific
Write Specific
Assume all “glue logic” delays are 10 ns

43. SRAM “Glue Logic” Propagation delay on ADDR to CE’ Upper-most bits/
Address Decode PLD
CPU
External
Memory Chip
Chip Enable (CE)
M-bits /
Address Bus (Abus)
Address (in)
N-bits /
Data Bus (Dbus)
Data (in/out)
Glue Logic
Propagation delays on R/W’ and CLK changing OE’ and WE’
R/W’
Output Enable (OE)
CLK
Write Enable (WE)
For the notes example: assume all glue logic delays are 10
In HW 5, you will be given an ABLE file that describes all the “glue logic”. Use ISPLever to get timings for each signal.

44. Successive Synchronous Read Cycles (with numbers)

45. Successive Synchronous Read Cycles (with numbers)

46. Successive Synchronous Read Cycles (with numbers)

47. Successive Synchronous Read Cycles (with numbers)

48. Successive Synchronous Read Cycles (with numbers)

49. Successive Synchronous Read Cycles (with numbers)

50. Successive Synchronous Read Cycles (with numbers)

51. Successive Synchronous Write Cycles (with numbers)

52. Matching CPU with timing to an SRAM
All the prior timing specs were dependent on the CPU
A common problem is to search for an SRAM part that will satisfy the timing constraints the CPU has.

53. Matching our example CPU to an example SRAM
Description
Parameter
Value
Address access time
tAA
80 ns min
Chip enable access time
tCE
Output enable access time
tOE
20 ns min
Output hold from OE’/CE’ negation or address change
tOH
10 ns min
Output float delay following tOH
tOZ
10 ns max
Input (write) data setup time
tIS
30 ns min
Input (write) data hold time
tIH
Write pulse width
tWP
40 ns min
Address valid prior to memory write
tAW
90 ns min
Chip enable valid prior to memory write
tCW
Read Specific
Write Specific

54. Successive Synchronous Read Cycles (with numbers)
Where SRAM “thinks” CPU read occurs
Last of these 3 to take effect determines critical paths
Critical path analysis:
Consider: tOE, tAA, tCE
tOZ
Reads typically determine critical path. In writes the margins are bigger

55. Successive Synchronous Read Cycles (with numbers)
Where SRAM “thinks” CPU read occurs
If the SRAM read float delay (tOZ) exceeds the processor’s write data generation delay (tAD): A. bus fighting might occur B. the wrong value might be read by the processor C. metastability might occur D. all of the above E. none of the above
tOZ

56. Successive Synchronous Write Cycles (with numbers)

57. Timing Margin
If the nominal tCE for a CPU-memory interface is 50 ns, the speed of SRAM that should be utilized in order to provide a 10% read timing margin is: A. 45 ns B. 50 ns C. 55 ns D. 60 ns E. none of the above
Definition: The difference between the “nominal” memory performance required and performance of actual memory component chosen
Why a margin is needed: To accommodate normal variations that occur in device performance due to operating temperature, lot variations, etc.
What is a “safe” margin? Usually about 10% of the parameter in question
What is the consequence of insufficient margin? Unstable performance!

58. Example: Conclusions
This example illustrates the use of a 5 MHz (200 ns bus clock) CPU in conjunction with an 80 ns (tAA and tCE) SRAM
If a CPU (as specified) is interfaced to an SRAM (as specified), and the “glue logic” delay is 10 ns, then the following timing margins will be realized:
read timing margin: 40 ns
write timing margin: 100 ns

59. Cycle “Stretch” Problem: Not meeting timing requirements
One solution: Just slow the clock!
However this is wasteful
Observation: Limiting timing factor when the clock is high
Alternative Solution: Make the clocker high time longer or “stretch the cycle”
20 ns normal cycle
Ex: 10ns “normal” high time
+ 1 cycle of stretch (20ns additional)

60. Homework Practice Draw read cycle followed by write cycle CPU tCY
Value
tCY
100 ns
tAD
30 ns
tAH
10 ns
tRS
20 ns
tRH
tDD
40 ns
tWH
tWZ
SRAM
Value
tAA
20 ns min
tCE
tOE
10 ns min
tOH
0 ns min
tOZ
30 ns max
tIS
tIH
tWP
tAW
tCW
3-B