1. BNL electronics: first tests
Progress report
15 Dec 2009, CERN

2. BNL TPC ASIC IC85 Technology: CMOS 0.25mm – 2.5 V Power 43 mW
MiM capacitor and silicide block resistor options
Power 43 mW
Front-End Channels 32
charge preamplifier
2nd order shaping amplifier
peak detector
timing detector
Integrated calibration capacitor 250 fF (s=0.1%)
Shaping time 600 ns
Channel gain 15mV/fC to 32mV/fC

3. ASIC IC85 Time and Amplitude Measuring Chain
When an event occurs above threshold the discriminator fires and
the peak and timing detectors are enabled
At the same time the peak and timing detectors of the two neighbor channels are enabled
The events in the three channels are processed for peak amplitude and peak timing
The two corresponding voltages are stored for each channel
DATA
Trigger
Ramp
Event
Shaped pulse
Comparator
Peak detector
Time detector

4. Timing: Tdelay scan Shown for Tdelay = 150 ns Pulser Amplitude 105 e
Trigger
Pulser
Tdelay
s=3.3 mV
T, mV

5. Timing calibration: chip A channel 8
needed
1mV = 3.23 ns

6. On-chip zero suppression
Amplitude Time
Trigger ID
3263
3264
3265
3266
3267 …
3281
3282
Automatic recording of neighbor strips when a channel exceeds hardware threshold
Strip addresses
Empty event
Testbeam data file run26
136K triggered events
7.5 Mb ascii
would be much smaller in binary

7. mMega + Double mesh
VDmesh 650 V
Vmesh 420 V 
Low Gain 3·103

8. Stand alone run26 triggered by scintillators, no silicon
Vdreif 1800 V
Vtop V
Vbott 750 V
Vmesh 420 V
chip A
chip B
Channels 13 1nd 18 are not connected to the chamber

9. Total number of strips fired in event no clustering
Total number of events
2 strip events

10. 2 strip events one of three channels missing
Bin 9 – 27 entries
in 3 cluster events this channel fired 2807 times
There are rare cases when 2 neighbors are missing

11. Analysis cuts Looking for a single cluster per event
Cluster width 3≤width≤6
Timing cuts
for a channel with maximum amplitude in a cluster
0.3<time<0.5
Amplitude cut: only hardware cut of 0.35
75 ns
no timing calibration
built-in ramp

12. Landau

13. Summary
BNL electronics based on ASIC IC85 tested with a pulser and with the beam at H6
Built-in ramp is very shallow to be replaced with an external one
Sparking prevent from running at high gain
Each channel to be calibrated separately on both timing and amplitude
Plan
Event Display
Mapping is simple here))
Resolution with Silicon