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EE 597G/CSE 578A Final Project

Published bySharyl Stone Modified over 6 years ago

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Presentation on theme: "EE 597G/CSE 578A Final Project"— Presentation transcript:

1 EE 597G/CSE 578A Final Project
Phase Locked Loop Han-Wei Chen & Ming-Wei Liu

2 Outline Specification VCO PFD Charge Pump Divider Layout Post-Sim

3 PLL Spec Input Signal Square Wave 12.5 MHz Output Signal Sine Wave
0.3 V to 3.2 V Vdd Gnd 3.3V Locked Speed 6u sec

4 Voltage Control Oscillator

5 VCO -- Ring Oscillator

6 VCO – Delay Cell

7 VCO

8 VCO Layout

9 VCO Post-Sim

10 Phase Frequency Detector

11 PFD

12 PFD

13 Charge Pump

14 Charging

15 Discharging

16 Divider

17 Divider

18 Simulation Results – Schematic Level

19 Overall Layout

20 Layout

21 Post-Sim

22 END~

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