Presentation is loading. Please wait.

Presentation is loading. Please wait.

Hans Krüger, University of Bonn

Similar presentations


Presentation on theme: "Hans Krüger, University of Bonn"— Presentation transcript:

1 Hans Krüger, University of Bonn
DHP 0.1 Submission Hans Krüger, University of Bonn

2 Overview ~4000 µm ~2000 µm H. Krüger, March 3, 2010

3 DHP 0.1 chip submission – done!
Implementation 90 nm IBM CMOS ($ MPW + $ C4 bumps) 32 inputs, 2 mm x 4 mm chip size (half of final chip) C4 solder bumps, 200 µm pitch (+ wire bonds) Features max. number of pixel rows: 1024 (256 Switcher channels) raw memory storage: two frames (2048 rows) common mode and static or dynamic (max. 16 frames average) pedestal correction offset compensation memory for DCD simple sequencer for Switcher control (no strobe gate support) two independent PLL blocks (fVCO = 900 MHz – 2.3 GHz): digital core + DCD/Switcher timing (nom. 1.6 GHz, div by [4,8,16] outputs) data serializer + Gbit link Gbit CML data output driver, AURORA 8B/10B link layer protocol DAC, ADC, band gap reference (U Barcelona) test circuits H. Krüger, March 3, 2010

4 Interconnect Issues Wire-bond IOs + area pads for C4 connected in parallel however layouts are required to have either WB passivation openings or C4 openings (although on different layers) we decided to submit layout with bump bond support Test setup preparation Bump bond adapter (including DCD footprint) Adapter PCB FPGA board (ML505 evaluation board) supporting RocketIO for DHP data output Flex kapton cable with repeater (optional) Documentation H. Krüger, March 3, 2010

5 DHP Test / Prototype Hardware
Stand-alone DHP test wire bond DHP (packaged?) debug I/O connectors on PCB  not possible, no WB version available Combined DCD-DHP test + small matrix r/o different matrices + bump bond adapter Large matrix r/o place DHP instead of DCD-RO chip small number of LVDS lines + some LVCMOS on flat ribbon cable SATA + or custom flex for gigabit data output (CML) DHP wire bond PCB ML-505 board SW 128 x 8(16) matrix V5 FPGA USB DCD DHP bump bond adapter adapter PCB PCIe need RocketIO for DHP r/o (AURORA support: at least V4FX or V5) SW SW SW SW 768 x 160 (120, 180) matrix DCD DHP DCD DHP DCD DHP adapter PCB H. Krüger, March 3, 2010


Download ppt "Hans Krüger, University of Bonn"

Similar presentations


Ads by Google