1. 8086 MICROPROCESSOR ARCHITECTURE & SEGMENTATION
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2. Multiplexed address & data pin
Multiplexed address & status pins
Select Minimum/ maximum mode
Multplexed address and data bus
Interrupt Pins

3. S4 S3 Segment Register ES 1 SS CS or none DS
A19/S6, A18/S5, A17/S4, A16/S3 S4 S3
Segment Register ES 1 SS
CS or none DS

4. BHE/S7 BHE A0 Word/Byte Access Whole word from even address 1
Whole word from even address 1
Upper byte from/ to odd address
Lower byte from/ to odd address
None

5. QS1, QS0 QS1 QS0 Status No operation 1 1st byte of op-code queue
No operation 1
1st byte of op-code queue
Empty queue
Subsequent byte of op-code queue

6. S0, S1, S2 S2 S1 S0 Status Interrupt Acknowledge 1 I/O read I/O write
Interrupt Acknowledge 1
I/O read
I/O write
Halt
Op-code Fetch
Memory Read
Memory Write
Passive

9. Flags Carry flag Overflow Parity flag Direction Auxiliary flag
Interrupt enable
Zero
Trap
Sign
6 are status flags
3 are control flag

10. BIU registers (20 bit adder) EU registers ES Extra Segment CS
8086 Programmer’s Model ES
Extra Segment
BIU registers
(20 bit adder) CS
Code Segment SS
Stack Segment DS
Data Segment IP
Instruction Pointer
EU registers AX AH AL
Accumulator BX BH BL
Base Register CX CH CL
Count Register DX DH DL
Data Register SP
Stack Pointer BP
Base Pointer SI
Source Index Register DI
Destination Index Register
FLAGS

11. 8086/88 internal registers 16 bits (2 bytes each)
AX, BX, CX and DX are two
bytes wide and each byte can
be accessed separately
These registers are used as
memory pointers.
Flags will be discussed later
Segment registers are used
as base address for a segment
in the 1 M byte of memory

15. Memory Address Generation
Intel
Memory Address Generation
The BIU has a dedicated adder for determining physical memory addresses
Offset Value (16 bits)
Segment Register (16 bits)
Adder
Physical Address (20 Bits)

16. Byte
end of code segment
3FFFF
Next instruction byte to be fetch
Physical address
30123
0123
Start of code segment
30000
CS: 30000 +
IP: =
Physical address
Physical Address generation for code segment

17. Byte
Top of Stack
end of code segment
6FFFF
SP = FFE0
6FFE0 H
Physical address
0123
Start of stack segment
60000 H
SS: 60000 +
SP: FFE0 =
Physical address FFE0
Physical Address generation for stack segment

18. Fig a) Non-pipelined execution of 3 instructions
F D E F D E F D E I1 I1 I1 I2 I2 I2 I3 I3 I3
Clock cycle
Fig b) Pipelined execution of 3 instructions F I1 I2 I3 I4 I5
F - Fetch I4 I1 I2 I3
D - Decode D E I1 I2 I3
E - Execute
Clock cycle

19. Operating modes of 8086 Microprocessor
8086 can be operated in two modes-
Minimum Mode
Maximum Mode
In minimum mode all control signals are generated by 8086 itself, so it is used in single processor system
In miximum mode all control signals are generated by bus controller 8288 and not by the processor 8086, so it is used in multiprocessor system.
The pin 33 MN/MX is used to set minimum mode or maximum mode of 8086 and also the function of pin no 24 to 31 will change as per the selected mode.

20. 8284 Pin Diagram:

21. 8284 Block Diagram: x1 AEN1 CSYNC F / C Clock OSC Clock Logic x2 EF1
PCLK
RDY1
AEN1
Ready Logic
READY
RDY2
AEN2
Reset Logic
RESET
RES

22. 8284 Connected to 8086 Mp 8284 X1 Ready X2 8086 Microprocessor AEN1
CLK
8284
F/C
Reset
RDY1
RDY2
RES R
+ 5 V
RESET KEY C

23. 8288 BUS CONTROLLER 1 2 3 4 5 6 7 8 9 10 20 19 18 17 16 15 14 13 12 11
Vcc S0 S2
MCE/PDEN
DEN
CEN
INTA
IORC
AIOWC
IOWC
IOB
CLK S1
DT/R
ALE
AEN
MRDC
AMWC
MWTC
GND
the 8288 is a 20-pin chip specially designed to provide all the control signals when the 8088/86 is in maximum mode. The input and output signals are described below.

24. MRDC
MWTC
AMWC
IORC
AIOWC
INTA S0 S1 S2
Bus
Command
Logic
AEN
CEN
CLK
IOB
DT/ R
DEN
ALE
MCE / PDEN
Control
Signals
Logic

25. Input signals

26. Pin Diagram of 74LS245:

27. Pin Diagram of 74LS245:

28. Function of 74LS245:

29. 8086 System Minimum mode
(74LS373)
(74LS245)

30. Processor Timing Diagram of 8086 (Minimum Mode) for Memory or I/O Read
CLOCK __
DT/R
ALE
AD15 - AD0
A15 - A0
D0 – D15 (from memory)
A19/S6 - A16/S3
A19 - A16
S6 - S3 __
IO/M
if I/O ACCESS this is HIGH, if MEMORY ACCESS this is LOW
____ RD
______
DEN

31. Processor Timing Diagram of 8086 (Minimum Mode) for Memory or I/O Write
CLOCK __
DT/R
ALE
AD15 - AD0
A15 - A0
D15 - D0 (from memory)
A19/S6 - A16/S3
A19 - A16
S6 - S3 __
IO/M
if I/O ACCESS this is HIGH, if MEMORY ACCESS this is LOW
____ WR
______
DEN

32. 8086 System Maximum Mode

33. Processor Timing Diagram of 8086(Maximum Mode) for Memory or I/O Read
CLOCK __
DT/R
ALE
D0-D15
AD15- AD0
A15 - A0
S2-S0
S2-S0 Active
S2-S0 Inacive
A19/S6 - A16/S3
A19 - A16
S6 - S3
MDRC/IORC
______
DEN

34. Processor Timing Diagram of 8086(Maximum Mode) for Memory or I/O Write
CLOCK __
DT/R
ALE
D0-D15
AD15- AD0
A15 - A0
S2-S0
S2-S0 Active
S2-S0 Inacive
A19/S6 - A16/S3
A19 - A16
S6 - S3
MWTC &IOWC
AMWC/AIOWC
______
DEN
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