1. WWiSE Group Partial Proposal on Turbo Codes
August 13, 2004
Airgo Networks, Bermai, Broadcom, Conexant, STMicroelectronics, Texas Instruments
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2. WWiSE contributors and contact information
Airgo Networks: VK Jones,
Bermai: Neil Hamady,
Broadcom: Jason Trachewsky,
Conexant: Michael Seals,
STMicroelectronics: George Vlantis,
Texas Instruments: Sean Coffey,
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3. Contents Overview of partial proposal Motivation for advanced coding
Specification of turbo code
Performance results
Summary
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4. Overview of partial proposal
The WWiSE complete proposal contains an optional LDPC code to enable maximum coverage and robustness
FEC coding fits into the system design in a modular way, and in principle any high-performance code could be used instead of the LDPC code
This partial proposal highlights an alternative choice for optional advanced code
The system proposed is identical to the WWiSE complete proposal in all respects except that the optional LDPC code is replaced by the turbo code described here
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5. Motivation for advanced coding
Advanced coding translates into higher achievable throughput at the same robustness
In particular, in most configurations the BCC of rate ¾ and turbo code of rate 5/6 have approximately the same performance
Thus advanced coding enables a rate increase from ¾ to 5/6 without robustness penalty
At any given rate, advanced coding enhances coverage and robustness
In addition, the modularity of the design means that the advantages carry over to every MIMO configuration and channel bandwidth
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6. Transmitter block diagram
Add pilots
Turbo encoder, puncturer
Interpol., filtering, limiter
MIMO interleaver
Symbol mapper
Upconverter, amplifier
IFFT
D/A
Add cyclic extension (guard)
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7. These are the constituent codes used in the 3GPP/UMTS standard encoder
Turbo encoder
Systematic bit
1+D +D3
g(D) =
Parity bit 0
1+D2+D3
Turbo
interleaver
1+D +D3
1+D2+D3
g(D) =
Parity bit 1
These are the constituent codes used in the 3GPP/UMTS standard encoder
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8. Turbo code frame format
The data payload is padded to reach a multiple of 512 bits
The result is divided into blocks of 2048 bits and 512 bits
Number of 512 bit blocks is in the range 1-4
All 512 bit blocks are placed at end of frame
Each block is encoded as a separate turbo codeword
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9. Turbo interleaver design
Two interleavers are proposed, one for each supported block size: 2048 and 512 bits
Each interleaver is a contention-free inter-window shuffle interleaver
Designed to minimize memory contention when code is decoded in parallel
Equivalent performance to 3GPP/UMTS interleavers
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10. Puncturer Parity bits are punctured at regular intervals
Puncture intervals:
Systematic & tail bits are not punctured; pad bits are punctured
All code rates are easily derivable from mother code
Other puncturing patterns and setups also work well
Code rate
Puncture interval
2/3 4
3/4 6
5/6 10
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11. Puncturing tail codewords
Tailing codewords, i.e., codewords of length 512 information bits, are punctured differently, to a lower code rate
This facilitates low latency decoding: tail codeword blocks are shorter and can be decoded with fewer iterations, without affecting operating point
Puncture intervals for tail blocks:
Code rate
Puncture interval
2/3 2
3/4 3
5/6
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12. Parallelization of turbo decoders
Divide trellis into a number of (possibly overlapping) segments and decode each in parallel
Any reasonable number of iterations can be achieved without affecting latency
End-of-packet latency:
To achieve full gains of turbo or any iterative code, it is possible to taper codeword length and rate at end of packet
High throughput naturally requires longer packets and Block Ack
. . .
Block 1
Block 3
Block 2
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13. Complexity
Compare to state complexity of 64-state BCC decoding equivalent throughput
System assumptions: M-state constituent codes, I iterations, soft-in soft-out algorithm extra cost factor of a, BCC duty factor of b
Decoder must process 2 x 2 x I x b trellis transitions (I iterations, 2 constituent codes, forward-backward for each, less duty factor), each of which costs aM/64 as much
Overall complexity is 4I abM/64 times as much as 64-state code
E.g., with M = 8, I = 7, a = 1.5, b = 0.7, we have times the state complexity
This does not account for other differences such as memory requirements and interleaver complexity
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14. Performance results
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15. Simulation setup All combinations of: Channels B, D, AWGN
20 MHz and 40 MHz
Rate ¾ and rate 5/6
BCC and turbo code
All simulations under ideal conditions
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16. Channel model B NLOS, 20 MHz
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17. Channel model B NLOS, 40 MHz
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18. Channel model D NLOS, 20 MHz
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19. Channel model D NLOS, 40 MHz
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20. AWGN, 20 MHz
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21. AWGN, 40 MHz
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22. References IEEE 802.11 documents:
IEEE / n, “WWiSE group PHY and MAC specification,” M. Singh, B. Edwards et al.
IEEE / n, “WWiSE proposal response to functional requirements and comparison criteria,” C. Hansen et al.
IEEE / n, “WWiSE partial proposal on turbo codes: specification,” S. Pope et al.
Parallelization:
4. K. Blankenship, B. Classon, and V. Desai, “High-throughput turbo decoding techniques for 4G,” Int. Conf. on 3G Wireless & Beyond, 2002.
5. E. Yeo, B. Nikolic, and V. Anantharam, “Iterative decoder architectures,” IEEE Communications Magazine, August 2003, pp
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23. References, contd.
6. Z. Wang, Z. Chi, and K. K. Parhi, “Area-efficient high-speed decoding schemes for turbo decoders,” IEEE Trans. VLSI Systems, vol. 10, no. 6, pp , Dec. 2002
S. Yoon and Y. Bar-Ness, “A parallel MAP algorithm for low latency turbo decoding,” IEEE Communications Letters, vol. 6, no. 7, pp , July 2002
Interleavers:
8. A. Nimbalker, K. Blankenship, B. Classon, T. Fuja, and D. Costello, “Inter-window shuffle interleavers for high-throughput turbo decoding,” Proc. Int. Symp. on Turbo Codes, 2003.
9. A. Nimbalker, K. Blankenship, B. Classon , T. Fuja, and D. Costello, “Contention-free interleavers,” Proc. Int. Symp. on Info. Theory, 2004.
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