1. WWiSE Group Partial Proposal on Turbo Codes
September 15, 2004
Airgo Networks, Bermai, Broadcom, Conexant, Realtek, STMicroelectronics, Texas Instruments
S. Coffey, et al., WWiSE group

2. WWiSE contributors and contact information
Airgo Networks: VK Jones,
Bermai: Neil Hamady,
Broadcom: Jason Trachewsky,
Conexant: Michael Seals,
Realtek: Stephan ten Brink,
STMicroelectronics: George Vlantis,
Texas Instruments: Sean Coffey,
S. Coffey, et al., WWiSE group

3. Contents Overview of partial proposal Motivation for advanced coding
Specification of turbo code
Performance results
Summary
S. Coffey, et al., WWiSE group

4. Transmitter block diagram
Add pilots
Turbo encoder, puncturer
Interpol., filtering, limiter
MIMO interleaver
Symbol mapper
Upconverter, amplifier
IFFT
D/A
Add cyclic extension (guard)
S. Coffey, et al., WWiSE group

5. Overview of partial proposal
WWiSE complete proposal contains optional LDPC code
FEC coding is a distinct module
In principle any high-performance code could be used instead of the LDPC code
This partial proposal discusses an alternative choice for optional advanced code
System proposed is identical to the WWiSE complete proposal in all respects except that the optional LDPC code is replaced by the turbo code described here
S. Coffey, et al., WWiSE group

6. Motivation for advanced coding
Higher achievable throughput at the same robustness
Capacity difference between rate ¾ and rate 5/6 with MMSE, 64-QAM is 3 dB
So any code that achieves 3 dB gain enables a rate increase from ¾ to 5/6: an 11% increase without robustness penalty
Compare rates 5/6 and 7/8: 2 dB difference for a 5% increase
Viability of 2x2 MIMO, BCC, rate ¾ in any mode implies similar robustness of 2x2 MIMO, new code, rate 5/6
S. Coffey, et al., WWiSE group

7. Motivation for advanced coding
In addition:
Better coding enhances coverage and robustness
Provides partial alternative to increased number of receive chains or high performance MIMO detection
Advantages carry over to all MIMO configurations and channel bandwidths
S. Coffey, et al., WWiSE group

8. Specification of turbo code
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9. Turbo encoder
Uses the constituent codes used in the 3GPP/UMTS standard encoder:
Parity bit 0
Parity bit 1
1+D +D3
1+D2+D3
g(D) =
Turbo
interleaver
Systematic bit
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10. Turbo code frame format
Data payload is padded to a multiple of 512 bits
Result is divided into blocks of 2048 bits and 512 bits
Number of 512 bit blocks is in the range 1-4
All 512 bit blocks are placed at end of frame
Each block is encoded as a separate turbo codeword
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11. Turbo code frame format, contd.
E.g., 4000 byte packet has approximately 15 blocks of length 2048, 1-4 of length 512
At 135 Mbps, 2048 bit blocks span 5 OFDM symbols; 512 bit blocks span 2 OFDM symbols
S. Coffey, et al., WWiSE group

12. Turbo interleaver design
Two interleavers are proposed, one for each supported block size: 2048 and 512 bits
Though algorithmically generated, implementations will hardwire interleavers, so number of block sizes should be minimized
Each interleaver is a contention-free inter-window shuffle interleaver
Designed to minimize memory contention in parallelized decoding
Equivalent performance to 3GPP/UMTS interleavers
S. Coffey, et al., WWiSE group

13. Puncturer Parity bits are punctured at regular intervals:
Systematic & tail bits not punctured; pad bits are
All code rates are easily derivable from mother code 10
5/6 6
3/4 4
2/3
Puncture interval
Code rate
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14. Puncturing tail codewords
Tailing codewords, i.e., codewords of length 512 information bits, are punctured to a lower code rate
This facilitates low latency decoding: tail codeword blocks are lower rate and can be decoded with fewer iterations, without affecting operating point
Puncture intervals for tail blocks: 3
5/6
3/4 2
2/3
Puncture interval
Code rate
S. Coffey, et al., WWiSE group

15. Parallelization of turbo decoders
Divide trellis into a number of (possibly overlapping) segments and decode each in parallel
Any reasonable number of iterations can be achieved without affecting latency
End-of-packet latency:
Tailing codewords can be decoded with fewer iterations
. . .
Block 1
Block 3
Block 2
S. Coffey, et al., WWiSE group

16. Complexity
Compare to state complexity of 64-state BCC decoding equivalent throughput
System assumptions: M-state constituent codes, I iterations, soft-in soft-out algorithm extra cost factor of a, BCC duty factor of b
Decoder must process 2 x 2 x I x b trellis transitions (I iterations, 2 constituent codes, forward-backward for each, less duty factor), each of which costs aM/64 as much
Overall complexity is 4I abM/64 times as much as 64-state code
E.g., with M = 8, I = 7, a = 1.5, b = 0.7, we have times the state complexity
This does not account for other differences such as memory requirements and interleaver complexity
S. Coffey, et al., WWiSE group

17. Performance results
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18. Simulation setup All combinations of:
Channels B, D, AWGN
20 MHz and 40 MHz
Rate ¾ and rate 5/6
BCC and turbo code
All simulations under ideal conditions
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19. AWGN, 20 MHz
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20. AWGN, 40 MHz
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21. Channel model B NLOS, 20 MHz
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22. Channel model B NLOS, 40 MHz
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23. Channel model D NLOS, 20 MHz
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24. Channel model D NLOS, 40 MHz
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25. Turbo and LDPC codes
Turbo codes have a more extensive and stable literature, build on Viterbi decoding, have straightforward encoders
LDPC codes have more flexibility, which may in principle be used to allow code design matched to decoder structure; more amenable to analysis
To first order, both give the same performance tradeoffs
S. Coffey, et al., WWiSE group

26. Conclusions
Turbo code compensates for code rate increase to 5/6 from ¾
Very well studied, extensive literature on performance and implementation
Latency at end of packet may be handled by tailing; applicable to LDPC codes also
Generally similar issues and tradeoffs as LDPC codes
S. Coffey, et al., WWiSE group

27. References IEEE 802.11 documents:
IEEE / n, “WWiSE group PHY and MAC specification,” M. Singh, B. Edwards et al.
IEEE / n, “WWiSE proposal response to functional requirements and comparison criteria,” C. Hansen et al.
IEEE / n, “WWiSE partial proposal on turbo codes: specification,” S. Pope et al.
Parallelization:
4. K. Blankenship, B. Classon, and V. Desai, “High-throughput turbo decoding techniques for 4G,” Int. Conf. on 3G Wireless & Beyond, 2002.
5. E. Yeo, B. Nikolic, and V. Anantharam, “Iterative decoder architectures,” IEEE Communications Magazine, August 2003, pp
S. Coffey, et al., WWiSE group

28. References, contd.
6. Z. Wang, Z. Chi, and K. K. Parhi, “Area-efficient high-speed decoding schemes for turbo decoders,” IEEE Trans. VLSI Systems, vol. 10, no. 6, pp , Dec. 2002
S. Yoon and Y. Bar-Ness, “A parallel MAP algorithm for low latency turbo decoding,” IEEE Communications Letters, vol. 6, no. 7, pp , July 2002
Interleavers:
8. A. Nimbalker, K. Blankenship, B. Classon, T. Fuja, and D. Costello, “Inter-window shuffle interleavers for high-throughput turbo decoding,” Proc. Int. Symp. on Turbo Codes, 2003.
9. A. Nimbalker, K. Blankenship, B. Classon , T. Fuja, and D. Costello, “Contention-free interleavers,” Proc. Int. Symp. on Info. Theory, 2004.
S. Coffey, et al., WWiSE group