1. Upgrade of the ALICE ITS
ALICE-USA Upgrade Discussions, 16 May 2013
L. Musa, CERN

2. New ITS Design goals
1. Improve impact parameter resolution by a factor of ~3
Get closer to IP (position of first layer): 39mm 22mm
Reduce material budget: X/X0 /layer: ~1.14%  ~ 0.3% (for inner layers)
Reduce pixel size
currently 50mm x 425mm
monolithic pixels  O(20mm x 20mm),
hybrid pixels  state-of-the-art O(50mm x 50mm)
2. Improve tracking efficiency and pT resolution at low pT
Increase granularity: 6 layers  7 layers , reduce pixel size
3. Fast readout
readout of Pb-Pb interactions at > 50 kHz and pp interactions at ~ MHz
4. Fast insertion/removal for yearly maintenance
possibility to replace non functioning detector modules during yearly shutdown

3. Includes safety factor ~ 4
Upgrade options
Two design options have being studied
7 layers of pixel detectors (baseline)
3 inner layers of pixel detectors and 4 outer layers of strip detectors
Option B
4 layers of strips
Option A
7 layers of pixels
3 layers of pixels
Pixels: O(20x20µm2 – 50 x 50µm2)
700 krad/ 1013 neq
Includes safety factor ~ 4
Pixels: O( 20x20µm2 – 50 x 50µm2)
Strips: 95 µm x 2 cm, double sided

4. Improvement of impact parameter resolution
x 5
x 3
Simulations for two upgrade layouts
Option A: 7 pixel layers
Resolutions: srf = 4 mm, sz = 4 mm for all layers
Material budget: X/X0 = 0.3% for all layers
Option B: 3 layers of pixels + 4 layers of strips
Resolutions: srf = 4 mm, sz = 4 mm for pixels srf = 20 mm, sz = 830 mm for strips
Material budget: X/X0 = 0.3% for pixels X/X0 = 0.83% for strips
radial positions (cm): 2.2, 2.8, 3.6, 20, 22, 41, 43
Same for both layouts

5. New ITS (baseline) Inner Barrel: 3 layers Outer Barrel: 4layers
Detector module (Stave) consists of
Carbon fibber support (space frame)
Cooling unit
Flexible printed circuit
Pixel Chip (CMOS pixel sensors)
25 G-pixel camera, 10 m2

6. Inner Barrel (IB): 3 layers pixels
Radial position (mm): 22,28,36
Length in z (mm): 270
Nr. of staves: 12, 16, 20
Nr. of chips/stave: 9
Nr. of chips/layer: 108, 144, 180
Material thickness: ~ 0.3% X0
Throughput: < 200 Mbit / seccm2
Outer Barrel (OB): 4 layers pixels
Radial position (mm): 200, 220, 410, 430
Length in z (mm): 843, 1475
Nr. of staves: 48, 52, 96, 102
Nr. of chips/stave: 56, 56, 98, 98
Nr. of chips/layer: 2688, 2912, 9408, 9996
Material thickness: ~ 0.8% X0
Throughput: < 6 Mbit / seccm2

7. COLUMN DISCRIMINATORS
CMOS Pixel Sensors
Ionizing Particle
ROLLING SHUTTER
Pixel Array
Row Address Decoder
Res Addr
COLUMN DISCRIMINATORS
Address
Generator
SCANNER & ENCODER

8. CMOS Pixel Sensors Study radiation hardness (TID and SEE)
Limitations of classical MAPS can be overcome with TowerJazz CIS process (deep p-well feature)
Development of MAPS detectors using
Tower/Jazz 0.18 µm CIS technology:
Improved TID resistance due to smaller technology node
Available with high resistivity (1-5k Ωcm) epitaxial layer up to 18 µm (substantial depletion at 1-2V)
Special quadruple-well available to shield PMOS transistors (allows in-pixel truly CMOS circuitry)
(R. Turchetta – RAL)
Study radiation hardness (TID and SEE)
Study/optimize charge collection performance and readout architecture

9. Pixel chip - R&D with TowerJazz technology
R&D with TowerJazz CIS process in 2011/12 (3 MPW runs)
What has been established so far
Adequate radiation hardness
Good charge collection ( detection) efficiency for pixel ~ 20μmx20μm
R&D will continue till end 2014, with the following objectives
Improve signal/noise ratio
Optimization of charge-collection diode
Increase resistivity and thickness of epi-layer
apply large reverse-bias voltage  lower capacitance,smaller cluster size
Study different front-end circuit and readout architectures
Reduce power consumption
Reduce integration/readout time
Circuit/layout optimization for high yield and stiching
 Submission in Mar/Apr 2013: Engineering Run (full reticle ~ 7 cm2)

10. Pixel chip - R&D with TowerJazz technology
Charge collection efficiencies (before/after irradiation) presented in CDR
Many new results:
example of detection efficiency measurement (Explorer chip) at PS test beam
Results from December 2012 test beam. More to come from recent test beam at DESY
4 layer self-consistent telescope at PS
Fake hit rate is estimated from laboratory noise measurements
Very high efficiencies at low fake hit rates!

11. Stave assembly R&D on interconnection technology Flex-on-flex
Flip-chip mounting

12. INNER BARREL Inner Barrel (IB) Inner Layers Stave
The Inner Barrel consists of the three innermost layers:
Inner Layers
layer 0, layer 1 and layer 2.
Stave
Flexible Printed Circuit (FPC) or Flex.
Pixel Chip
Coldplate
Spaceframe

13. ∆ (Tchip-Twater)<8°C
INNER BARREL
Baseline for ITS simulation Inner Barrel Stave (TDR) IB
1.4 g
"Carbon Plate with Embedded Pipes"
1) CF Fleece 8g/m2 (th=0,02mm)
2) K13D2U (th=0,07mm)
3) Polyimide tube (ID=1.024mm)
4) AmecTremasol FGS 003 (th=0.03mm)
Test results WATER
∆ (Tchip-Twater)<8°C

14. INNER BARREL 14

15. INNER BARREL
Structural Sandwich
Layer 0
Layer 1
Prototype
Layer 2

16. Baseline for ITS simulation Outer Barrel Stave (TDR)
OUTER BARREL (OB)
Baseline for ITS simulation Outer Barrel Stave (TDR)
Middle Layers
Two inner layers of the Outer Barrel, i.e. layers 3 and layer 4
Outer Layers
Two outermost layers, i.e. layer 5 and layer 6
Stave
Spaceframe
Cold Plate
Cold Plate
Half-Stave
Each half-stave will consists of a number of modules glued on a common cold plate
Module
Each module consists of a hybrid integrated circuit, i.e. a number of pixel chips (e.g. 2 x 7) bonded on a flexible printed circuit, which might be glued on a carbon ply

17. PROTOTYPE Outer barrel staves LAYER 5,6 length 1526mm. Weight 33,6g

18. Baseline for Outer Barrel Stave
Preliminary test results
∆ (Tchip-Twater)<13°C
this consider a reworkable interface for module dismounting

19. Outer Barrel Outer Layers Stave Middle Layers Layer 3-4 Spaceframe
Cold Plate
Cold Plate
Layer 5-6
Module
Module
Middle Layers

20. ITS COLLABORATION CERN China (Wuhan) Czech Republic (Prague)
France IN2P3-CNRS (Strasbourg, Grenoble)
Italy INFN (Bari, Cagliari, Catania, Frascati, Padova, Roma, Torino, Trieste)
Korea (Inha, Pusan, Yonsei)
Netherland (NIKHEF/Utrecht)
Pakistan (COMSATS)
Russia (St. Petersburg)
Slovakia (Kosice IEP)
Thailand (Nakhon Ratchasima SUT)
UK STFC (Daresbury, RAL), Univ. Birmingham, Univ. Liverpool
Ukraine (Kharkov, Kiev)
US (LBNL, ?)

21. PROJECT ORGANIZATION PL: L. Musa, DPL: Vito Manzari, TC: vacant
Institute Board: PL, DPL, TC, SPL, Team Leaders
Project Coordination: PL, DPL, TC, SPL, SRC, Upgrade WP Coordinators
Maintenance and Operation: PL, DPL, TC, SPL, QAC, Experts
Upgrade Work Packages Convener(s)
1. Physics performance studies A. Dainese
2. Simulation and reconstruction I. Belikov, M. Masera
3. PIXEL Chip L. Musa (ad interim)
4. Wafer post-processing and test P. Riedler
Pixel chip characterization M. Mager
Inner Layers A. Di Mauro
Middle Layers
Outer Layers P. Kuijer, V. Manzari
Mechanics, Cooling and Integration C. Gargiulo
Readout Electronics P. Giubilato
SPL = Sub Project Leaders (SPD, SDD, SSD)
QAC = Quality Assur. Coordinator

22. SPARE SLIDES

23. ITS BARRELS

24. TPC Bore
Outer Barrel
Inner Barrel
INTEGRATION

25. ~3,7m
~1,7m
~0,9m
18,8°
~0,6m
ITS

26. PROJECT ORGANIZATION CERN China Czech Republic & Slovakia France Italy
Pixel chip design, characterization and series test
Wafers procurement, qualification and post-processing
Inner Layers
Mechanics, Cooling and Integration
Readout electronics
Simulation and reconstruction, physics
China
Pixel chip design and series test
Assembly and test of hybrid integrated circuit (Outer Barrel)
Czech Republic
&
Slovakia
Characterization of components for radiation hardness
Readout Electronics
France
Pixel chip design and characterization
Assembly and test of hybrid integrated circuit (Outer Barrel)
Mechanics
Italy
Pixel chip design, characterization and test
Outer Layers
Mechanics and cooling

27. Project Organization Korea Netherlands Pakistan Russia Thailand UK
Pixel chip characterization and series test
Assembly and test of hybrid integrated circuit
Physics
Netherlands
Outer Layers
Readout electronics (power distribution and regulation)
Pakistan
Pixel chip (TCAD) simulations
Readout electronics
Russia
Pixel chip characterization
Mechanics and cooling
Thailand
Wafers qualification (doping profile), thinning and dicing
Development of pseudo-dummy chips and silicon micro-channels
Characterization of pixel chip
Simulation and reconstruction, physics UK
Pixel chip design and characterization
Assembly and hybrid integrated circuit and staves
Ukraine
Development of flexible printed circuit US
Middle Layers