1. Digital Logic & Design
Dr. Waseem Ikram
Lecture No. 28

2. Synchronous Decade Counter

3. Timing diagram of a Synchronous Decade Counter

4. 74HC163 4-bit Synchronous Counter

5. Timing diagram of the 74HC163 Synchronous counter

6. Cascaded Decade Counters

7. Timing diagram of a Cascaded Decade Counter

8. 74HC163 configured as Mod-7 counter

9. The timing diagram of a truncated Mod-7 Counter

10. 74HC161 configured as Mod-9 counter

11. Timing diagram of a 74HC161 configured as Mod-9 counter

12. 74HC163 counters connected for cascaded truncated count sequence

13. Up-counting sequence of a 3-bit Synchronous Counter
Clock Pulse Q2 Q1 Q0 1 2 3 4 5 6 7

14. Down-counting sequence of a 3-bit Synchronous Counter
Clock Pulse Q2 Q1 Q0 1 2 3 4 5 6 7

15. Synchronous Decade Counter
Recap
Down Counters
Synchronous Counter
3-bit counter
4-bit counter
Synchronous Decade Counter

16. Synchronous Counter
Decade Counter timing diagram (fig 1)
Mod-n Synchronous Counter
IC 74HC163 Mod-16 Counter (fig 2)
IC 74HC160 Mod-10 Counter

17. Cascading & Truncated Sequence Counters
Cascading Counters (fig 3)
IC counters with truncated seq. (fig 4)
IC 74x161 counter with Asyn. Clear (fig 5)
Cascading counters with truncated sequence (fig 6)

18. Up-Down Counters
Up-Down Counter (tab 1)