1. EKT 221 – Counters

2. Synchronous Counter
• To eliminate the "ripple" effects, use a common clock for each flip-flop and a combinational circuit to generate the next state.
• For an up-counter, use an incrementer

3. Synchronous Counter

4. Synchronous Counter • Internal Logic – XOR complements each bit
– AND chain causes complement of a bit if all bits toward LSB from it equal 1
• Count Enable
– Forces all outputs of AND chain to 0 to “hold” the state
• Carry Out
– Added as part of incrementer
– Connect to Count Enable of additional 4-bit counters to form larger counters

5. Synchronous Counter
Serial Gating

6. Counter with Parallel Load
Add path for input data
enabled for Load = 1
Add logic to :
Disable count logic for Load = 1
Disable feedback from outputs for Load = 1
Enable count logic for Load = 0 & Count = 1

7. Counter with Parallel Load
The resulting function table :
Load
Count
Action
Hold Stored Value 1
Count Up Stored Value X
Load D

9. Converting parallel load counter into sync. BCD counter
Connect an external AND gate to LOAD
Start with all-zero output (0000)
COUNT input always HIGH (1)
BCD counts from 0000 to 1001
To ensure LOAD = 1, Q0 and Q3 must be HIGH
LOAD input (D0  D3) = 0000

10. Converting parallel load counter into sync. BCD counter

12. Synchronous BCD Counter
Y = 1, when present state = 1001
FF input equations
Obtained from next – state values
Simplify using K – map
1010  1111 (don’t care)
Y = Q1Q8

13. Counting Modulo N
A counter that goes through a repeated sequence of N states
Maximum decimal number to be counted :
If Mod 16, then the max decimal number is 15
If Mod N = 2n then the max decimal counted is N-1
To determine the required number of flip-flops:
n flip-flop 2n output = Mod N

14. Counting Modulo 7
Use a synchronous 4 – bit binary counter with a synchronous load and clear
LOAD – detect count “6” and load “0”
Gives count of ( 0,1,2,3,4,5,6,0,1….)
Using don’t care for states above 0110, detect number “6” when LOAD = Q2.Q1

15. Counting Modulo 7

16. Counting Modulo 6 : special requirement
Requirement : synchronously preset “9” on RESET and LOAD “9” on terminal count “14”
Use a synchronous, 4 – bit counter with a synchronous LOAD
Use LOAD signal to :
preset count to “9”
detect count “14”
Give count of (9,10,11,12,13,14,9,10,…)

17. Counting Modulo 6 : special requirement

18. Arbitrary Count Sequence
Design a counter with six states as in table below

19. Arbitrary Count Sequence
2 states are not included : 011 and 111
Simplified equations :

20. Arbitrary Count Sequence
Logic diagram of the counter

21. Cascaded Counters

22. CASCADED COUNTERS
Two cascaded counters (all J and K inputs are HIGH).

23. A modulus-100 counter using two cascaded decade counters.

24. Three cascaded decade counters forming a divide-by-1000 frequency divider with intermediate divide- by-10 and divide-by-100 outputs.

25. Example: Determine the overall modulus of the two cascaded counter for (a) and (b)
For (a) the overall modulus for the 3 counter configuration is 8 x 12 x 16 = 1536 for (b) the overall modulus for the 4 counter configuration is 10 x 4 x 7 x 5 = 1400

26. A divide-by-100 counter using two 74LS160 decade counters.

27. A divide-by-40,000 counter using 74HC161 4-bit binary counters
A divide-by-40,000 counter using 74HC161 4-bit binary counters. Note that each of the parallel data inputs is shown in binary order (the right-most bit D0 is the LSB in each counter).

28. Counter Applications

29. Simplified logic diagram for a 12-hour digital clock.

30. Logic diagram of typical divide-by-60 counter using 74LS160A synchronous decade counters. Note that the outputs are in binary order (the right-most bit is the LSB).

31. Logic diagram for hours counter and decoders
Logic diagram for hours counter and decoders. Note that on the counter inputs and outputs, the right-most bit is the LSB.

32. Functional block diagram for parking garage control.

33. Logic diagram for modulus-100 up/down counter for automobile parking control.

34. Assignment Folder Contents
10: -3, -4, -5, -6, -7, -8, -9

35. THE END