1. EEL 3705 / 3705L Digital Logic Design
Spring 2007 Instructor: Dr. Michael Frank Module #14: Modular Sequential Design (Thanks to Dr. Perry for some slides)

2. Frequently-Used Modular Sequential Components
Memory elements:
Flip-flops & Registers (already covered)
Synchronous ROMs (w. registered I/O ports)
RAMs (asynchronous & synchronous)
Simple, common state machines:
Counters (plain binary and mod-n)
Accumulators
Shift registers (left/right, w. serial & parallel I/O)

3. Insert more slides here…
Most of the remaining slides in this module need to be deleted, and replaced with some slides giving examples of modular sequential designs of the above components, and explaining their functions…

4. Dr. Perry’s Slides
Following are some old slides by Dr. Perry on Counters and Shift Registers, left over from previous semesters…

5. FSM Examples

6. Example– 2-bit Up Counter
State Diagram
Clock is implied

7. Example – 2-bit Up Counter
State Table
State Value Assignment
Let
S0 = 00
S1 = 01
S2 = 10
S3 = 11 ps ns y S0 S1 S2 1 S3 2 3
Output Vector
Let S0 = reset state

8. Example – 2-bit Up Counter
Truth Table
ps1
ps0
ns1
ns0 y1 y0 1

9. Example – 2-bit Up Counter
Excitation Equations

10. Moore FSM State Equations Next State Present State Output Vector
Input Vector
Clock
Feedback
Path
Reset
State Equations

11. Logic Diagram Reg Block F Logic Y Vector H Logic
No X Vector in this Example
No H Logic needed

12. Logic Diagram

13. Flash Animation

14. Example 3– 2-bit Down Counter
State Diagram
Clock is implied

15. Example – 2-bit Down Counter
State Table
Let
S0 = 00
S1 = 01
S2 = 10
S3 = 11 ps ns y S0 S3 S2 3 S1 2 1
Let S0 = reset state

16. Example – 2-bit Down Counter
Truth Table
ps1
ps0
ns1
ns0 y1 y0 1

17. Example – 2-bit Down Counter
Excitation Equations

18. Recall Moore FSM State Equations Next State Present State
Output Vector
Input Vector
Clock
Feedback
Path
Reset
State Equations

19. Logic Diagram Reg Block F Logic Y Vector H Logic
No X Vector in this Example

20. Logic Diagram

21. Example 4 – 2-bit Up/Down Counter
State Diagram

22. Example – 2-bit Up/Down Counter
State Diagram
Shorthand Notation

23. Example – 2-bit Up/Down Counter
State Table ps ns
upn y S0 S1 S3 S2 1 2 3
Let
S0 = 00
S1 = 01
S2 = 10
S3 = 11
Let S0 = reset state

24. Example – 2-bit Up/Down Counter
Truth Table
upn
ps1
ps0
ns1
ns0 y1 y0 1

25. Example – 2-bit Up/Down Counter
Excitation Equations

26. Recall Moore FSM State Equations Next State Present State
Output Vector
Input Vector
Clock
Feedback
Path
Reset
State Equations

27. Logic Diagram
Reg Block
X Vector
F Logic
Y Vector
H Logic

28. Logic Diagram

29. Example 5– 3-bit Arbitrary Counter
Design a 3-bit arbitrary counter that will count in the following sequence
3,2,3,1,2,3
If a state is not used reset it to state zero.
How may states do we have?
How many registers do we need?
How many bits do we need for Y?

30. Example 5– 3-bit Arbitrary Counter
State Diagram

31. Example – Arbitrary 3-bit Counter
State Table
Assign State Values
Let
S0 = 000
S1 = 001
S2 = 010
S3 = 011
S4 = 100
S5 = 101
S6 = 110
S7 = 111 ps ns y S0 S1 3 S2 2 S3 S4 1 S5 S6 S7
Let S0 = reset state

32. Develop Truth Table

33. Example – 2-bit Arbitrary Counter
Develop Excitation Equations -- F Logic

34. Develop Excitation Equations for Y

35. Example – 2-bit Arbitrary Counter
Excitation Equations -- H Logic

36. Recall Moore FSM State Equations Next State Present State
Output Vector
Input Vector
Clock
Feedback
Path
Reset
State Equations

37. Logic Circuit H
REG F

38. Logic Circuit

39. Simulation

40. Example 5– 2-bit Up/Down Counter with Active Low Enable and Synchronous RESET (SRESET)
State Diagram
Clock is implied

41. Example – 2-bit Up/Down Counter with Enable and SRESET
Functional Table
srn en
upn
Function d
Synchronous Reset (sreset) 1
Hold
Count Up
Count Down
Highest Level of Priority
Lowest Level of Priority

42. State Table
Srn En
upn ns d S0 1 ps
ps+1
ps -1

43. Truth Table (5 variables!!)
Although, we could design this circuit directly from the truth table
we will use design partitioning.

44. Moore FSM Architecture
Next
State
Present
State
Output Vector
Input Vector
Feedback
Path

45. to create the “new” design.
Partitioned Design
srn
We have en
Srn En ns d S0 1 PS
Count
Note, with the partitioned design we can “reuse” already designed submodules
to create the “new” design.

46. Top Level Block Diagram

47. UP/Down Logic
Logic Circuit
Symbol

48. Register Block
Symbol
Logic Circuit

49. 2 Bit 4x1 Mux
Circuit
Symbol

50. 1-bit 4x1 Mux
Logic Circuit
Symbol

51. 1-bit 2x1 Mux
Logic Circuit
Symbol

52. Top Level Block Diagram

53. Simulation

54. Example 6 – FSM Controller
State Diagram

55. Truth Table for NS
Truth Table

56. Kmaps for NS1 and NS0
NS1
NS0

57. Truth Table and Equations for Y
Recall, Moore FSM, so Y will
Not be a function of T
By Inspection

58. Logic Circuit H
REG F

59. Simulation

60. Modular Sequential Logic

61. Shift Registers
Logic Design which manipulates the bit position of binary data by shifting it to the left or right.
Major application
Serial Data to Parallel Data converters

62. Example Design a three-bit shift register with the following functions
Synchronous Reset (sreset) 1
Shift Right
Shift Left
No Shift

63. Partitioned Design

64. No Shift Equations and Circuit

65. Shift Left Equations and Circuit

66. Shift Right Equations and Circuit

67. Synchronous Reset Module

68. Registers

69. Total Design