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Part III A workshop by Dr. Junaid Ahmed Zubairi
VLSI DESIGN USING VHDL Part III A workshop by Dr. Junaid Ahmed Zubairi
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Workshop References VHDL by Amos Zaslavsky (http://www.pet.ac.il )
Fundamentals of Digital Design by Brown and Vranesic, McGraw Hill Altera Training Modules
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Synchronous Circuits Use a process to describe a flip flop
VHDL signals are static so no need to assign q<= q All flip flops used by Altera have asynchronous reset Do not use asynchronous preset
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Designing a Counter You can implement a counter using a process with statements as below: if clk’event and clk=‘1’ then count <= (count+1) mod LIMIT Where LIMIT is selected by you and Count is an inout port of type integer with range 0 to LIMIT-1
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Gated Clock Code
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Signals Translate to Hardware
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With Variables….
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Safer Method It is safer to use the first style without variables as variables may get converted into static storage nodes
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Summary Only use asynchronous signals and clock in the sensitivity list If asynch signals are present, deal with them before the sync condition Each assignment in the sync process infers a flip flop
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Bad Coding Example
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Correct Coding Style
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If You need the combo to be synchronized with the clock
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Initialization Signals can only be initialized in the declarative part
Signal enable:std_logic := ‘1’; Do not initialize the signals in the execution path of the process However, initializations may be ignored because FPGA components may have some well defined initial values Instead of initialization, use the real hardware reset or preset (NOT BOTH) and activate it in the beginning
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LPM LPM is Library of Parameterized modules
Using modules from LPM, you do not have to write VHDL architecture for some sub-systems For example, instead of doing an up-and-down counter in VHDL, you may reuse lpm_counter with generic map statements in the architecture body or use RAM module
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LPM Resources Quartus_dir\eda\sim_lib
VHDL source files are 220model.vhd and 220pack.vhd Quartus contains lpm.pdf file
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