1. SLAC Timing System Overview
Mike Stanek
SLAC Accelerator Dept.
Operations Group
16-Sep-2003
9/16/03
SLAC Timing System Futures Workshop

2. SLAC Aerial View
The SLAC Timing System delivers triggers to timed devices on each beam line and experiment, except for SPEAR, which has its own independent timing system.

3. SLAC Timing System Specifications
SLC Design:
(~1982)
Resolution: <10 nSec
- Jitter: <1 nSec
- RF distribution
PEP – II:
(~1998)
- Resolution: 2.1 nSec
- Jitter: 20 pSec
SLAC’s timing requirements have evolved over the years.
9/16/03
SLAC Timing System Futures Workshop

4. Synchronization Requirements
AC Line Voltage
(2 zero crossings x 3 phase 60 hz = 360 hz)
Damping Ring RF bucket
(8.5 MHz revolution harmonic)
Linac Main Drive Line
(476 MHz)
PEP RF buckets
(3492 buckets, 136 KHz rev. harmonic)
Down in the Sector Zero Alcove, the Sequence Generator puts out a 360 Hz waveform, synchronous with zero-crossings of 3-phase AC from the power lines.
All timed devices are synchronized to occur repetitively at the same place on the power cycle in order to eliminate power-line related instabilities.
The stability of this basic 2.78 milliSecond time unit varies with the spectral purity of the AC sine wave. One microsecond jitter is common, as viewed on a short term basis.
But power line jitter doesn’t affect operation of the LINAC, since each machine cycle takes place within 2.78 milliSeconds.
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SLAC Timing System Futures Workshop

5. SLAC Timing System Futures Workshop
Devices
Klystron Modulator thyratrons
Pulsed kicker magnets
Beam diagnostics (BPM, Gated ADC’s, Toroids)
For devices requiring < 10 nsec precision, specialized hardware has been developed
TGAS (gun triggers)
Vernier Delay Unit – 100 psec (Damping Ring kickers)
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SLAC Timing System Futures Workshop

6. Fiducials (Master Clock pulses)
Linac – at 360 Hz
one “double amplitude” 476 MHz cycle inserted on Main Drive Line RF distribution
PEP-II
360 Hz “injection” fiducial – sync’ed to Linac
136 KHz “ring” fiducial – from PEP Master Oscillator (also locked to Linac M.O.)
One (two) “double period” cycle
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SLAC Timing System Futures Workshop

7. Waveforms: 476 MHz with FIDUCIALS
LINAC
The LINAC (SLC-style) Fiducial is a single large-amplitude cycle of 476 MHz. The FIDO Fiducial detection circuit is amplitude-triggered. The FIDO also divides 476 MHz by four, and feeds 119 MHz to the SLC-style PDU’s.
The PEP-2 Style Fiducial is a single cycle of 238 MHz superimposed on the 476 MHz sine wave. There is no FIDO in PEP-2; the PEP-2 PDU’s receive 476 MHz directly.
PEP - 2
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SLAC Timing System Futures Workshop

8. Trigger Generation, simplified
This is simplified?
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SLAC Timing System Futures Workshop

9. Sector 0 Trigger Generation, oversimplified
The Master Oscillator puts out 476 MHz, which is phase shifted and amplified, then cabled to the Fiducial Generator, where an amplitude-modulated Fiducial is superimposed at 360 Hz.
The 476 with Fiducial goes to the Main Drive Line, which supplies triggers to the LINAC and the rest of SLAC.
Locally, 476 is coupled off to drive Sectors Zero, One, and the Damping Rings.
9/16/03
SLAC Timing System Futures Workshop

10. Trigger Generation, simplified1 5 2 4
Main path of 476 MHz is shown across the top, from Master Oscillator to Main Drive Line.
Several critical components have hot spares standing by: Master Amplifier, Fiducial Generator, Sequence Generator.
A phase lock loop surrounds the amps and the Fiducial Generator.
The SLC Countdown chassis has an 8.5 MHz output which drives the Master Trigger Generator (SLC) for Damping Ring Synchronization.
The PEP Pattern Generator is closely coupled with the SLC Master Trigger Generator, providing phasing for PEP Injection.
The NIM Fiducial Generator (no longer actively in the system) is used locally to observe the phasing of the Fiducial going out on the Main Drive Line.
9/16/03
SLAC Timing System Futures Workshop 3

11. SLAC Timing System Futures Workshop
Linac Sector Timing
476 MHz + fiducial coupled from MDL
Divide-by-four ( 119 MHz)
8.4 nsec “ticks” (SLC specs)
Convert “double amplitude” fiducial to “missing cycle” of 119 MHz.
FIDucial Output chassis (FIDO)
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SLAC Timing System Futures Workshop

12. LINAC Timing Typical Sector
Divide by 4
 8.4 nsec ticks
476 MHz with Fiducial is coupled off the Main Drive Line in each LINAC sector, then split.
One side drives the Sub Booster; the other side is amplified and fed to the FIDO.
The FIDO divides by 4, and superimposes the missing pulse Fiducial on the 119 MHz output, which drives the PDU’s.
But take a look at how the 119 is distributed: the Sector 10 FIDO drives Sector 9’s CAMAC Crate 4, and Sector 10’s Crate 2 and Crate 3.
This has been a great help in rapidly diagnosing Control System malfunctions between the Micro/CAMAC sub-system and the Timing Sub-system.
CAMAC
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SLAC Timing System Futures Workshop

13. SLAC Timing System Futures Workshop
LINAC Rack, Front
476 MHz with Fiducial from the Main Drive Line is split, then amplified by the FIDO RF AMP to drive the FIDO, which divides by 4 and superimposes a missing pulse Fiducial on the 119 MHz output.
The FIDO 119 outputs are cabled via ¼” heliax to the PDU’s in the LINAC CAMAC timed crates.
The MKSU receives its timing signals from PIOP’s located in the CAMAC crates.
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SLAC Timing System Futures Workshop

14. SLAC Timing System Futures Workshop
LINAC Rack, Rear
The rear view of the FIAT rack shows the splitter near the Main Drive Line. ¼” Heliax cabling connects the outputs to the Sub Booster and to the FIDO RF Amp. The FIDO RF Amp drives the FIDO.
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SLAC Timing System Futures Workshop

15. SLAC Timing System Futures Workshop
MDL Coupled Output
An even closer view of the splitter area.
Loose connections on the T-1000 splitter have been a source of intermittent missing Fiducials in the past.
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SLAC Timing System Futures Workshop

16. Waveforms: 119 MHz and NIM Pulse
FIDO Output
The FIDO receives 476 MHz with an amplitude Fiducial, and puts out a pulse train of 119 MHz with a missing pulse at Fiducial time.
119 MHz from the FIDO is coupled to the SLC PDU through 1/4” Heliax cable. The PDU has sixteen pulse channels, with each channel’s pulse repetition frequency and delay programmable through CAMAC.
PDU Output
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SLAC Timing System Futures Workshop

17. SLAC Timing System Futures Workshop
NLC Test Accelerator
Uses Linac Fiducials
Distributed to NLCTA via fiber optic link, from the downstream end of the Linac to the Research Yard.
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SLAC Timing System Futures Workshop

18. SLAC Timing System Futures Workshop
Fiber Optic Xmtr
Stand on tippy-toes to see the status LED’s in the Fiber Optic Transmitter located on the top of Sector 30’s Sub Booster.
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SLAC Timing System Futures Workshop

19. SLAC Timing System Futures Workshop
Fiber Optic Link
The Fiber Optic Transmitter located on top of the Sub - Booster at the head end of Sector 30 sends 476 MHz with an amplitude Fiducial across a length of buried Fiber Optic cable to Bldg 407, located between End Station A and the FFTB beamline in the Research Yard.
In the locked Laser Room, the Fiber Optic Receiver converts the optical waveform back to an electrical signal.
This output drives an Amplifier and Splitter Chassis in the same rack.
One output is now terminated (it used to drive a local FIDO). The other output is cabled over to the NLCTA in End Station B, Bldg 062.
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SLAC Timing System Futures Workshop

20. SLAC Timing System Futures Workshop
NLCTA Triggers
476 MHz from the Fiber Optic Receiver in Bldg 407 drives the 476 MHz Distribution Chassis in Bldg 062.
The unterminated outputs drive FIDO’s and local RF Reference electronics.
Some of the FIDO outputs directly drive PDU’s; some of them are chained through 119 MHz Distribution units to provide more outputs.
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SLAC Timing System Futures Workshop

21. PEP-II fiducial generation
PEP-II uses two types of fiducials, generated in Region 8
360 Hz, sync’ed to Linac fiducials for injection
136 KHz, sync’ed to PEP Master Oscillator for stored beam diagnostics and control
PEP Master Oscillator is (usually) locked to Linac Master Oscillator.
9/16/03
SLAC Timing System Futures Workshop

22. PEP – II Timing Generation
476 MHz from the Main Drive Line in Sector 30 is cabled to the Line Distribution Chassis in the PEP Control Room, and gets fed to the PEP-2 Fiducial Generator’s Fiducial Detection circuit, which puts out a 360 Hz pulse in sync with the LINAC (considered PEP-s Injector).
The PEP-2 Master Oscillator, also located in the PEP Control Room, provides the RF for the PEP Klystrons and the PEP Timing System. Its output feeds the Fiducial Generator’s Phase Lock circuit, as well as the Fiducial Generator, and the Ring Clock Generator.
The output of the Fiducial Generator is amplifed and split three ways. One output drives local timing modules in the PEP Control Room.
The other two outputs drive the TPLD’s (Timing Phase Lock and Distribution Chasses).
Power and Voltage monitors aid in remote diagnosis of timing problems.
9/16/03
SLAC Timing System Futures Workshop

23. PEP-II timing distribution
PEP has 2 RF distribution cables:
One WITH the fiducial superimposed
One WITHOUT fiducial (used by the RF systems)
In each PEP IR hall, the Timing distribution signal is compared and phase locked to the “RF only” signal.
9/16/03
SLAC Timing System Futures Workshop

24. PEP – 2 Timing Distribution
PEP MHz RF is generated by the PEP-2 Master Oscillator, and the Fiducial Generator imposes two Fiducials on the RF: one for Injection (LINAC synch) and one for Ring synch.
One Fiducial Generator’s output drives the TPLD in Region 8, which in turn drives Region 6, then 4 and finally Region 2 (BaBar).
Another Fiducial Generator output drives the TPLD in Region 10, which in turn feeds Region 12.
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SLAC Timing System Futures Workshop

25. Timing Phase Lock Distribution B.D.
The Timing Phase Lock Distribution chassis is constructed as a Phase Lock Loop. The input Timing Reference In is compared with the RF Reference In, and phase-shifted to track the RF Ref In.
Timing Reference 476 MHz with two Fiducials enters the TPLD and the RF level is monitored by a SAM. Next is the Phase Shifter, and a Digital Delay unit (controlled by the SCP).
The Fiducials are regenerated in the TPLD, and there are latches which trip if a Fiducial is missed.
The output is amplified, monitored, and split to drive the PLL, local CAMAC crates, and the next TPLD in the PEP Ring.
Graphic by E.L.Cisneros
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SLAC Timing System Futures Workshop

26. SLAC Timing System Futures Workshop
TPLD SCP Diagnostics 2
It’s possible to display histories of each analog channel.
The +24 Volt power supply has a diurnal variation, and so does the PLL Error signal. When one of these doesn’t correlate to the daily temperature fluctuation, it indicates a problem.
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SLAC Timing System Futures Workshop

27. “Instructions” for each Fiducial
Master Pattern Generator (microprocessor)
uses SLCnet cable to send 126 bits (x3) every fiducial pulse to remote micros
“PNET” band of SLCnet
“Pipelined” bits for the next 3 fiducials
MSB a.k.a. Beamcode or PP (pulsed pattern)
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SLAC Timing System Futures Workshop

28. SLAC Timing System Futures Workshop
Each bit has designated purpose, e.g.:
BPM data acquisition for specific application
No beam (gun trigger suppress)
Use this pulse for e- feedback data
HER injection
Fire the HER Injection tune-up dump kicker
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SLAC Timing System Futures Workshop

29. SLAC Timing System Futures Workshop
MPG multi-tasking
Linac Klystron maximum rate is 120 Hz (only uses 1/3 of available fiducials)
Other 240 fiducials can be labeled for other programs (NLCTA, Gun Test lab)
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SLAC Timing System Futures Workshop

30. MPG bit patterns determined by inputs from…
Machine Protection Systems
Algorithm processor micros
Direct inputs from older hardware
BaBar – stop injection
Operator requests
PEP injection system (BIC)
– which bucket to fill, and how much charge
– shared memory
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SLAC Timing System Futures Workshop

31. What happens at a remote micro?
Interrupt the micro
Translate 126 bit word  8 bit word
Broadcast to CAMAC crates
PDU (Programmable Delay Unit)
Combines Analog (119 MHz + fiducial) with Digital (beamcode info)
16 programmable countdown channels
Generate trigger on CAMAC upper backplane
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SLAC Timing System Futures Workshop

32. SLAC Timing System Futures Workshop
PDU flexibility
Each channel generates output trigger:
Adjustable over 2.7 msec range (8.4 nsec steps)
Or using (n-1) or (n-2) fiducial with pipeline info, that range can be shifted up to 5.4 msec early
On specific combinations of PNET bits
“On demand” for BPM data acquisition
(YY mode)
On every fiducial, independent of PNET bits
On a subset of fiducials (multiples of 10 hz)
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SLAC Timing System Futures Workshop

33. Sixteen channels per PDU;
PDU – SLC Type
119 MHz from the FIDO drives a Counter, and the detected missing pulse Fiducial resets the counter.
Count length is set under SCP control via CAMAC.
If RE-USE is active, the counter is reloaded for each cycle.
The counter’s outputs are buffered and sent to the CAMAC Upper Timing Backplane as Differential ECL, where they are distributed to each CAMAC slot.
The front panel “X” LED flashes when the PDU is addressed by CAMAC.
Front Panel LEDs indicate whether the FIDUCIAL is DETECTed, and whether there has been a MISSING FIDUCIAL.
Note: these LEDs are under CAMAC control, not “real time” indications.
Sixteen channels per PDU;
One channel shown
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SLAC Timing System Futures Workshop

34. SLAC Timing System Futures Workshop
LINAC Timed Crate
119 MHz from the FIDO is cabled via ¼” Heliax to the PDU.
1/119 MHz = 8.4 nSec, the LINAC Timing System “tick.”
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SLAC Timing System Futures Workshop

35. SLAC Timing System Futures Workshop
PEP micro & CAMAC
PEP PDU
Direct 476 MHz + fiducial input (2.1 nsec ticks)
Programmable for
Injection mode or Ring mode (136 KHz)
HER or LER
Continuous or Fixed length Pulse Train
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SLAC Timing System Futures Workshop

36. SLAC Timing System Futures Workshop
The combination of Micro code
(both MPG and remote micros)
and PDU (and VDU) modules
flexibility
in generating triggers.
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SLAC Timing System Futures Workshop

37. An important feature: Synchronous data collection
BPM data can be acquired for a single e- pulse as it travels through the accelerator.
Correlation of Buffered BPM data (labeled with Pulse ID) can be used to make difficult measurements and diagnose accelerator instabilities.
Feedback systems can be “Cascaded”, to prevent overcorrection of errant trajectories.
9/16/03
SLAC Timing System Futures Workshop

38. PEP RF bucket synchronization
Generate a specially timed Linac Fiducial for each PEP bucket (3492)
i.e. shift the entire Linac timing
Beam to be injected is already stored in the Damping Ring ( msec store time)
Delaying the fiducial by “n” Damping Ring turns, we can hit 25% of the PEP buckets…
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SLAC Timing System Futures Workshop

39. SLAC Timing System Futures Workshop
How to figure out “n” ?
TPEP=3492 b TDR=56 b =(4*9*97)b =(4*2*7)b476
TPEP=(873/14)TDR
14 TPEP= 873 TDR
By changing the number of stored DR turns we inject into 873 different PEP buckets.
(1/4 of total 3492)
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SLAC Timing System Futures Workshop

40. SLAC Timing System Futures Workshop
If the desired bucket number (D) is known, MPG can calculate number of DR turns (R) to wait.
R= (D*686) mod 873
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SLAC Timing System Futures Workshop

41. How is the shifted fiducial created?
PEP Trigger Generator (PTG) module in an injector CAMAC crate:
Input bits from MPG (over PNET) tell it how many DR turns to delay.
Line locked gate from SLC MTG module (873 TDR wide)
476 MHz input (-> generates PEP bucket clock, period= 873 TDR)
Outputs fiducial pulse to SLC MTG for distribution on MDL.
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SLAC Timing System Futures Workshop

42. SLAC Timing System Futures Workshop
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SLAC Timing System Futures Workshop

43. What about the other ¾ of PEP buckets?
While beam is stored in DR, shift Linac Master oscillator -1, or +1, or +2 buckets of 476 MHz.
720 degree (476 MHz) Pulsed phase shifter in series with the Linac Master Oscillator. Programmed to shift phase based on special PNET bits from MPG.
DR extracted beam is locked to Linac RF – ramp phase slow enough to keep the beam stable
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SLAC Timing System Futures Workshop

44. Check to see if it worked…
Compare Linac fiducial with a PEP bucket 0 fiducial. (both signals are in MCC)
Difference should be predicted by MPG.
Time Difference Counter (TDC) circuit in injector PTG module, and in MPG crate.
MPG synchronization feedback.
MPG can correct for changes > 1 PEP bucket.
Can disable injection to PEP if not stable.
9/16/03
SLAC Timing System Futures Workshop

45. Some Common Timing Problems
RF signal degradation and noise
Poor cable connections
Sensitivity to temperature extremes
Bucket “jumps” in PEP timing system
One leg of the TDC comparison shifts wrt the other.
Often the beam has not shifted – just the measurement, but feedback still applies a correction.
Jitter is usually caused by power supply problems, although in the Sector Zero alcove, we did see one case of a BNC to LEMO adapter with a temperature co-efficient which caused a twice-yearly Bucket Jump.
FIDO-related failures include: the FIDO, the FIDO amp, the Splitter at the MDL coupler.
Poor connections and power supply problems seem to account for a large portion of Timing System troubles.
There is an occasional bucket jump which is traced to a bad PEP PDU in MCC.
Undocumented modifications are a challenge:
Example: users finish their experiment and disconnect equipment without terminating a line into 50 Ohms, and the reflections cause level shift and timing grief.
Example: modifications are made to the path of signal flow without notification, which makes troubleshooting interesting when Operations reports lost or jittery triggers.

46. SLAC Timing System Futures Workshop
References
Thanks to Duane Thompson (retired) of ESD –
(I borrowed many of his Power Point slides)
SLAC-PUB-3508 A New Timing System for the Stanford Linear Collider
SLAC-PUB-3476 The Design of a Semi-custom Integrated Circuit for the
SLAC SLC Timing Control System
PEP-II Injection Timing and Controls
SLAC-PUB-4231 Timing Stabilization for the SLC Electron Source
SLAC-PUB-4906 Timing and RF Synchronization for Filling PEP/SPEAR with The SLC Damping Rings
IEEE Trns A Programmable Delay Unit Incorporating a Semi- Nucl. Sci. Custom Integrated (Circuit PDU Write-up)
NS-34, No. 5, (1985)
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SLAC Timing System Futures Workshop

47. SLAC Timing System Futures Workshop
SLAC-CN-144 Pulse-to-Pulse Control of the LINAC with the new Controls System 
NSS A Vernier Delay Unit, W.B. Pierce
BD NN SLC Timing System (update in progress, Oct 2001)
SLACSpeak
Principles Of OPeration
Basic Users Guide
SLC Hardware Manual
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SLAC Timing System Futures Workshop