UCSD CSE and ECE Departments

UCSD CSE and ECE Departments
The ITRS Design Technology and System Drivers Roadmap: Process and Status Andrew B. Kahng UCSD CSE and ECE Departments

Agenda The ITRS, Design, and System Drivers Roadmaps
The Design Technology Working Group Roadmapping Examples Layout Density (“A-Factor”) Models MPU Driver Modeling Low-Power Design Technology Concluding Thoughts

The International Roadmap for Semiconductors
15-year technical outlook for 14 supplier industries and their respective technology areas 25-year projection of technology needs for emerging research devices and materials Drives research and funding agendas worldwide 5 regional associations (EU, Japan, Korea, Taiwan, USA), participants “Intended for technology assessment only and is without regard to any commercial considerations pertaining to individual products or equipment”

International Roadmap Committee
ITRS Global Structure International Roadmap Committee Coordination among Associations Policy Goal Schedule Coordination among ITWGs TWG ESIA Technology Needs, Potential Solutions in Near & Long Terms JEITA （STRJ) etc. KSIA FEP SIA ITWG Test Design TSIA

The ITWGs International Technology Working Groups (ITWGs) forecast technology requirements, potential solutions at 15-year horizon Emerging Devices, Emerging Materials: +10 more years outlook Each regional working group = industry + government + suppliers + consortia + academia System Drivers Design Process Integ, Devices & Structures Front End Processes Emerging Research Devices Emerging Research Materials Lithography Interconnect Factory Integration Assembly & Packaging Test and Test Equipment Metrology Yield Enhancement Modeling & Simulation Environment, Safety & Health RF/AMS Tech for Wireless Comm

The ITWGs System Drivers Design
International Technology Working Groups (ITWGs) forecast technology requirements, potential solutions at 15-year horizon Emerging Devices, Emerging Materials: +10 more years outlook Each regional working group = industry + government + suppliers + consortia + academia System Drivers Design Process Integ, Devices & Structures Front End Processes Emerging Research Devices Emerging Research Materials Lithography Interconnect Factory Integration Assembly & Packaging Test and Test Equipment Metrology Yield Enhancement Modeling & Simulation Environment, Safety & Health RF/AMS Tech for Wireless Comm

Design, System Drivers (2004-2011)
MTM roadmap MTM roadmap 1. Increasingly quantitative roadmap 2010 2009 2. Increasingly complete driver set MTM RF+AMS Driver start MTM RF+AMS Driver start RF+AMS Driver continued Updated Drivers (MPU, SoC,…) 2008 3. Increasing More Than Moore content MTM extension + iNEMI synch + SW !! 2007 MTM extension + iNEMI + SW !! More Than Moore (MTM) analysis + iNEMI Updated Consumer SOC and MPU Drivers Updated Consumer Stationary, Portable architecture, and Networking Drivers 2006 Consumer Stationary, Portable, Networking Drivers Updated Consumer Stationary, Portable, and Networking Drivers 2005 Consumer Stationary, Portable, Networking Drivers Upgraded DFM, SL, verification sections Power design technology roadmap Upgraded RF+AMS section Consumer Stationary, Portable Drivers 2004 Consumer Portable Driver Additional Design Metrics DFM Extension System level extension System Drivers Chapter Driver study Revised Design Metrics DFM extension Revised Design Technology Metrics Revised Design metrics Design Technology metrics Design Chapter Explore Design metrics 9

Design, System Drivers (2004-2011)
MTM roadmap MTM roadmap 1. Increasingly quantitative roadmap 2010 2009 2. Increasingly complete driver set MTM RF+AMS Driver start MTM RF+AMS Driver start RF+AMS Driver continued Updated Drivers (MPU, SoC,…) 2008 3. Increasing More Than Moore content MTM extension + iNEMI synch + SW !! 2007 MTM extension + iNEMI + SW !! More Than Moore (MTM) analysis + iNEMI Updated Consumer SOC and MPU Drivers Updated Consumer Stationary, Portable architecture, and Networking Drivers 2006 Consumer Stationary, Portable, Networking Drivers Updated Consumer Stationary, Portable, and Networking Drivers 2005 Consumer Stationary, Portable, Networking Drivers Upgraded DFM, SL, verification sections Power design technology roadmap Upgraded RF+AMS section Consumer Stationary, Portable Drivers 2004 Consumer Portable Driver Additional Design Metrics DFM Extension System level extension System Drivers Chapter Driver study Revised Design Metrics DFM extension Revised Design Technology Metrics Revised Design metrics Design Technology metrics Design Chapter Explore Design metrics 10

Chapter Structure DESIGN SYSTEM DRIVERS Overall Challenges
Detailed Technology Challenges Methodology System-Level Design Logical, Circuit, Physical Design Design Verification Design for Test Design for Manufacturability More Than Moore AMS/RF Design Appendices Variability roadmap Design Cost model Low-power design roadmap 3DIC SYSTEM DRIVERS Market Drivers SOC Driver SOC-Networking SOC-Consumer Portable SOC-Consumer Stationary Microprocessor (MPU) Driver Mixed-Signal Driver Embedded Memory Driver

Working Group Process Distributed operation: each chapter subsection is maintained by one or more regions, a subteam + owner Coordination, editing, etc. duties performed by ITWG chairs Always responding to cross-TWG issues Always trying to fill any identified gaps TSV-based 3DIC (parasitics 2007, design technology 2009) Hardware-related software development cost (2009) Low-power design technology roadmap (2011) Many interactions with designers, EDA technologists and researchers – your participation is welcome!!! Japan + USA SOC system driver models USA Density models + calibration Europe AMS/RF design

Design ITWG’s Current Grand Challenges
Rolled up into ITRS Executive Summary Near term ( 7 years out) Power management Design productivity Design for manufacturing Long term (8-15 years out) Management of leakage power Design of concurrent software Design for reliability and resilience

Key Messages = Advocacy for EDA, CAD
2001: “Cost of design is the greatest threat to continuation of the semiconductor roadmap” Design technology innovations must keep on schedule to contain design costs, power

Design Cost Model Model both hardware + software development costs
A. B. Kahng and G. Smith, “A New Design Cost Model for the 2001 ITRS“, Proc. ISQED, 2002 Model both hardware + software development costs Example cost elements (consumer SOC design) Salaries, licenses Mask set, probe card Design reuse, TAT Quantified productivity impacts of design technology improvements NRE, Complexity-dependent costs Design Technology Improvement Year Productivity Delta Productivity (Gates/Year/Designer) IC Implementation Suite 2001 63.60% 91K HW, 87K SW RTL Functional Verification Tool Suite 2003 37.50% 125K HW, 87K SW Transactional Modeling 2005 60% 200K HW, 250K SW Very Large Block Reuse 2007 200% 600K HW, 323K SW Homogeneous Parallel Processing 2009 100% HW, 100% SW 1200K HW, 646K SW Software Virtual Prototype 2011 300% SW 1200K HW, 2584K SW

EDA Impact on IC Design Cost
(2023) Supercomputer-Class Servers +100% HW, +75% SW productivity (2017) Heterogeneous (AMP) Parallel Proc +100% HW, +100% SW productivity (2013) Reusable Platform Blocks +200% HW, +100% SW productivity

EDA Impact on IC Design Cost
(2023) Supercomputer-Class Servers +100% HW, +75% SW productivity Design cost of SOC consumer portable chip in 2011 = $40M Without EDA technology advances from , the same chip would have cost $7.7B to design. (2017) Heterogeneous (AMP) Parallel Proc +100% HW, +100% SW productivity (2013) Reusable Platform Blocks +200% HW, +100% SW productivity

Key Messages = Advocacy for EDA, CAD
2001: “Cost of design is the greatest threat to continuation of the semiconductor roadmap” Design technology innovations must keep on schedule to contain design costs, power 2007: System-level techniques are ultimately crucial to managing power 2009: Software and system-level design productivity are critical challenges The design-manufacturing interface roadmap shifts from “manufacturability” to “variability” 2009: Design-based equivalent scaling is essential to continuation of Moore’s Law

Today: EDA and Design are Central to Roadmap
What is the max-length (global, semi-global) wire on chip? How much variability can designers tolerate? What scaling of leakage vs. drive is needed by key product drivers? How many unique cores in the SOC? ORTCs max chip power layout density defect density transistor count chip size #distinct cores #cores IO speed max on-chip freq 3D TSV parasitics product/market drivers Fundamental Models INTC CMP, R, C, MOL, Jmax PIDS Id,sat, Isd,leak CV/I,fT Design & System Drivers FEP Vt variation LITHO Mask cost, CD 3σ, pitch, overlay Test #cores, max IO freq #IOs, max power, thermal, TSV/3D roadmap A&P

Today: EDA and Design are Central to Roadmap
ORTCs max chip power layout density defect density transistor count chip size #distinct cores #cores IO speed max on-chip freq 3D TSV parasitics product/market drivers Fundamental Models INTC CMP, R, C, MOL, Jmax PIDS Id,sat, Isd,leak CV/I,fT Design & System Drivers FEP Vt variation LITHO Mask cost, CD 3σ, pitch, overlay Test #cores, max IO freq #IOs, max power, thermal, TSV/3D roadmap A&P

Heartbeat of the ITRS: Technology Nodes
Key metric of (density) progress: half-pitch (F) Metal-1 (M1) half-pitch scales by 0.7x 0.7 x 0.7 = 0.49  density doubles at each “technology node” Layer Normalizations to PM1 2009 2013 F 0.50 M1 Pitch (PM1) 1.00 M2 Pitch (PM2) 1.25 Contacted Poly Pitch (CPP) (Ppoly) 1.50 Fin Pitch (Pfin) -- 0.75 P/G Track Width Scaling in both X, Y dimensions

A-Factor Density Model (2009)
Models of SRAM (USRAM) and NAND2 (UNAND2) area with minimum-rule layouts [ISOCC09, ITRS 2009] 2Ppoly 3Ppoly NWell M1 Poly Contact Active 8PM2 5PM1 Ulogic = 3Ppoly  8PM2 = 180F calibrated 175F2 USRAM = 2Ppoly  5PM1 = 60F2

Introduction of FinFET (2013)
Models of SRAM (USRAM) and NAND2 (UNAND2) area using FinFET New layout bottleneck: Pfin Assumption: Pfin = 0.5 PM1 2Ppoly 3Ppoly Discrete fins 8PM2 5.6PM1 Ulogic = 3Ppoly  8PM2 = 180F calibrated 175F2 Ulogic = 2Ppoly  5.6PM1 = 67F2

Intel MPU Scaling Trends
[Sutter09] # of Transistors Clock Frequency Power Performance/CLK (ILP)

ITRS MPU Frequency Roadmap
before 2001 2001 ITRS 2007 ITRS 2011 ITRS Device speed only 41% / year Platform power limit 17% / year 8% / year Frequency (GHz) Device scaling limit 4% / year

ITRS MPU Frequency Roadmap
before 2001 2001 ITRS 2007 ITRS 2011 ITRS 41% / year 17% / year 8% / year Frequency (GHz) [Danowitz et al., Stanford CPUDB] 4% / year

MPU Transistor Density Scaling: Not Ideal !
“GAP” Actual data Transistor density (#transistors/mm2) A NEW IC DESIGN GAP: available density scaling vs. realized density scaling Non-ideal A-factor  larger cells, wires for reliability Uncore in architecture  small, distributed functions Year

A New IC Design Gap ?!? 1993 Design Productivity Gap (SEMATECH)
Transistors growing at 68%/yr Design productivity growing at 21%/yr [Cf. 2013 Design Capability Gap (UCSD) Available density growing at 2x/node Realizable density growing at 1.6x/node

2013 MPU Transistor Density Calibration
(1) Collected data Too optimistic (2) 2009 ITRS model (2x/node) (3) 2x/node till 2013; 1.6x/node beyond 2013; Tx count from 2009 model  Proposed (4) 1.6x/node from 2008; Tx count from Xeon X3350 (2008) (2) (3) (4) (1)

MPU Overheads OSRAM: peripheral circuits
core1 core2 Ouncore Ologic Accelerators core3 core4 Memory Controller OA-factor I/O interfaces OSRAM SRAM2 SRAM5 SRAM1 GPUs SRAM3 SRAM4 Ointegration OSRAM: peripheral circuits Ologic: placement and whitespace Ouncore: accelerators, memory, IO controller, system bus OA-factor: reliability, variability margins, large-sized and complex cells Ointegration: whitespace due to IP blocks, core, uncore integration

Overhead Values 2009: All overheads are fixed
2013: OA-factor and Ouncore scale at 1.25× per node 2009 model 2013 model Values Scaling Ologic 1.6 Fixed OSRAM 2.0 OA-factor N/A 1.12 1.25× /node Ouncore Ointegration 1.42 1.47 (bulk) 1.42 (FinFET)

Why Does Ointegration Increase?
Reasons for increase from 1.42 (from 2009 model) to 1.47 (in 2013 model) Products used to calibrate transistor count, density and area are different. Additional whitespace overhead for core, uncore integration In FinFETs (from 2016) Area utilization of SRAMs increases (higher A-factor) So, overhead decreases from 1.47 to 1.42

Summary of Changes to MPU Area Modeling
𝐴 𝑙𝑜𝑔𝑖𝑐 =# 𝑁 𝑙𝑜𝑔𝑖𝑐−𝑐𝑒𝑙𝑙 × U 𝑙𝑜𝑔𝑖𝑐 × 𝑂 𝑙𝑜𝑔𝑖𝑐 𝐴 𝑆𝑅𝐴𝑀 =# 𝑁 𝑆𝑅𝐴𝑀−𝑐𝑒𝑙𝑙 × U 𝑆𝑅𝐴𝑀 × 𝑂 𝑆𝑅𝐴𝑀 (2009 model) 𝐴 𝑙𝑜𝑔𝑖𝑐 =# 𝑁 𝑙𝑜𝑔𝑖𝑐−𝑐𝑒𝑙𝑙 × U 𝑙𝑜𝑔𝑖𝑐 × 𝑂 𝑙𝑜𝑔𝑖𝑐 × 𝑂 𝑢𝑛𝑐𝑜𝑟𝑒 × 𝑂 𝐴−𝑓𝑎𝑐𝑡𝑜𝑟 (2013 model) 𝐴 𝑆𝑅𝐴𝑀 =# 𝑁 𝑆𝑅𝐴𝑀−𝑐𝑒𝑙𝑙 × U 𝑆𝑅𝐴𝑀 × 𝑂 𝑆𝑅𝐴𝑀 × 𝑂 𝑢𝑛𝑐𝑜𝑟𝑒 × 𝑂 𝐴−𝑓𝑎𝑐𝑡𝑜𝑟 𝐴 𝑐ℎ𝑖𝑝 = (𝐴 𝑙𝑜𝑔𝑖𝑐 + 𝐴 𝑆𝑅𝐴𝑀 ) × 𝑂 𝑖𝑛𝑡𝑒𝑔𝑟𝑎𝑡𝑖𝑜𝑛 (no change between 2009 and 2013)

Power: The Grandest of Grand Challenges
Power and energy identified as the ITRS grand challenge  new Low-Power Design Technology roadmap (2011) J.-A. Carballo and A. B. Kahng, Future Fab Intl., Issue 40, Jan. 2012 Hardware-Software Co-partitioning at the behavioral level Architectural Heterogeneous Parallel processing Software Virtual prototype Many-core development tools Circuit Frequency island Near-threshold Asynchronous

Low-Power Design Roadmap
Power and energy identified as the grand challenge  low-power design roadmap (2011) Design Technology Improvement Year Improvements Description Dynamic Static Software Virtual Prototype 2011 1.23 1.20 Allow the programmer to develop software prior to silicon Frequency Islands 2013 1.26 1.00 Designing blocks that operate at different frequencies Near-Threshold Computing 2015 0.80 Lowering Vdd to mV Hardware/Software Co-Partitioning 2017 1.18 Hardware/software partitioning at the behavioral level based on power Heterogeneous Parallel Processing (AMP) 2019 Using multiple types of processors in a parallel computing architecture Many Core Software Development Tools 2021 Power-Aware Software 2023 1.21 Developing software using power consumption as a parameter Asynchronous Design 2025 Non-clock driven design Total 4.66 0.96

Low-Power Design Roadmap
Power and energy identified as the grand challenge  low-power design roadmap (2011) Design Technology Improvement Year Improvements Description Dynamic Static Software Virtual Prototype 2011 1.23 1.20 Allow the programmer to develop software prior to silicon Frequency Islands 2013 1.26 1.00 Designing blocks that operate at different frequencies Near-Threshold Computing 2015 0.80 Lowering Vdd to mV Hardware/Software Co-Partitioning 2017 1.18 Hardware/software partitioning at the behavioral level based on power Heterogeneous Parallel Processing (AMP) 2019 Using multiple types of processors in a parallel computing architecture Many Core Software Development Tools 2021 Power-Aware Software 2023 1.21 Developing software using power consumption as a parameter Asynchronous Design 2025 Non-clock driven design Total 4.66 0.96 SOC consumer portable chip in 2026: 2 billion logic gates Low-power DT reduces power from 43.9 W to 8.22 W

Many Warnings on Power in the Roadmap
E.g., power of mobile SOC-CP driver keeps increasing… … even if future low-power innovations are developed and deployed on time

“Dark Silicon” Prediction from ITRS 2001
ITRS 2001: Power gap  Decreasing logic content Amount of logic in SOC would have to drop to zero “Dark Silicon” already visible in ITRS 12 years ago

Future of the ITRS Design Roadmap
Past foundations of ITRS are shaky A-factors no longer constant Realization of 2X density scaling per node likely broken as of 2009 More Than Moore, 3D, “design-based equivalent scaling” are all acknowledgments of this Technology uncertainty is a major challenge to roadmapping of design technology requirements Patterning: EUV, directed self-assembly Cost: triple- and quadruple patterning Device: tunnel FETs, resistive RAMs … Design Capability Gap now clearly visible … So, what are the potential solutions?

Roadmap participation ↓
And Bigger Challenges Fewer resources but scope widens Roadmap is not anyone’s day job… New scope: MEMS, More Than Moore, 3DIC, … Greater automation, co-optimization is needed  “Living ITRS”? Risk of a “vicious cycle” Oligopolistic EDA industry Disaggregation and consolidation in industry Unwillingness to share “competitive” data Explosion of post-CMOS, post-optical technology options Need better communication across supplier industries design-manufacturing academia-industry Roadmap participation ↓ Roadmap value ↓

The Good News 2009 and 2010 EDA Roadmap Workshop
Dialogue among EDA/semiconductor companies and research consortia Analyze needs and status of EDA roadmapping Other efforts: CATRENE, DTC, SRC, SIGDA, DATC... Today, in this 15th year of the ITRS, Design Technology-based “equivalent scaling” is acknowledged as essential to the continued Moore’s Law scaling of semiconductor value

Acknowledgments Dr. Juan-Antonio Carballo Dr. Kwangok Jeong
Co-chair of Design ITWG since 2004 Dr. Kwangok Jeong A-factor, MPU model revisions in 2007 Dr. Sani Nassif Initiation of DFM roadmap in 2005; this invitation Tuck-Boon Chan, Siddhartha Nath, Wei-Ting Chan and Ilgweon Kang Invited paper preparation Many colleagues in NTRS/ITRS since 1996

Thank You!

Personal Mission: Evangelizing Value of EDA
“Cost of Design” (2001)

“Cost of Design” (2001) “Shared Red Bricks” (2001)

“Cost of Design” (2001) “Shared Red Bricks” (2001) “Design-based equivalent scaling” (2007)

“Cost of Design” (2001) “Shared Red Bricks” (2001) “Design-based equivalent scaling” (2007) “Holistic margin reduction” (2010)

SPARE SLIDES

Design for Manufacturing (DFM)
DFM section introduced in 2005 Requirements Potential Solutions Fundamental economic limitations Mask cost RET tools aware of circuit metrics Statistical leakage analysis and optimization tools Model-based physical verification … Lithography and variability limitations σVdd, σVth, critical dimension, … Early solutions for variability emerged as predicted Embedding of statistical methods in design flow is slower than expected (but viewed as inevitable)

DFM: Driven at all Abstraction Levels
Physical Device Gate Chip Bit Cell Circuit Array

Canonical Modeling: Δoutputs = model(Δinputs)
Variability-induced failures

Circuit-Level Impacts of Variability
Three key components of a digital CMOS design: SRAM bitcell, latch, inverter Simulate circuits under manufacturing variability Failure rates

Power Supply Dependent Failure Rates
Supply voltage is an important lever to reduce failure rates 10X reduction in failure rate Failure rates Power supply

Moore’s Law & More Than Moore (MTM)
More than Moore: Diversification More Moore: Miniaturization Combining SoC and SiP: Higher Value Systems Baseline CMOS: CPU, Memory, Logic Biochips Sensors Actuators HV Power Analog/RF Passives 130nm 90nm 65nm 45nm 32nm 22nm 16 nm . V Information Processing Digital content System-on-chip (SoC) Beyond CMOS Interacting with people and environment Non-digital content System-in-package (SiP)

Application – Function – Technology Interplay
“More-than-Moore” functions needed applications “More Moore” FOM lead markets designs and devices size, suitability design tools societal needs processes

Why a More Than Moore Roadmap ?
ITRS has demonstrated value of roadmapping for CMOS Identify pre-competitive research domains, enabling cooperation between industries, institutes and universities Sharing of R&D efforts Reduction of development costs and time Synchronize R&D and Manufacturing communities Increase resource efficiency through focus Promote market growth and job creation More Than Moore roadmapping offers a similar but more challenging opportunity First step: Propose a roadmapping methodology December 2010 white paper available at ITRS home page

“Necessary Conditions” for MTM Roadmap
Figures of merit (FOM) Converged / majority opinion regarding “laws of expected progress” trends that FOMs are expected to follow (LEP) Potential market of significant size inducing wide applicability of the technology (WAT) Willingness to share information (SHR) Existence of a community of players (ECO) Status assessment, Dec 2010

Design and System Drivers Chapters

“The Design Productivity Gap”
Potential Design Complexity and Designer Productivity Equivalent Added Complexity Logic Tr./Chip Tr./S.M. 68 %/Yr compounded Complexity growth rate 21 %/Yr compound Productivity growth rate 3 Yr. Design Third, this is the famous “Design Productivity Gap”. The number of available transistors increases by 58% / year compounded. But Design Technology increases the designer’s capability by only 21% / year. Therefore, the cost of design increases exponentially. The key: We need to use the silicon, but the product cost must be kept low. Product cost = design cost + silicon cost If design technology is not improving fast enough, how many gates can I get for $1 ? $3 ? $10 ? Year Technology Chip Complexity Frequency Staff Staff Cost* 250 nm M Tr MHz M 250 nm M Tr M 180 nm M Tr M nm M Tr M Source: SEMATECH $ 150 k / Staff Yr. (In 1997 Dollars)

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